Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Submicron Pattern Generation by Oxidation of Polysilicon

IP.com Disclosure Number: IPCOM000061099D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Chin, D: AUTHOR

Abstract

This article discusses a method of generating submicron patterns on silicon wafers beyond the lithographic unit defined by optical or electron beam lithography. It is a well known fact that state-of-art lithography has the limit of a minimum feature size of 0.7 um for proximity corrected optics and 0.5 um for electron beams. The only way to make smaller line widths was the sidewall spacer technology which utilizes anisotropic etching characteristics of reactive ion etching. The spacer technology, however, generates only a positive pattern which resides near another lithographically defined lines. As a result, several more masking steps are necessary to break the closed patterns either in circles or rectangles. In this disclosure, a negative pattern with line width down to 0.1 um was successfully made.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 89% of the total text.

Page 1 of 2

Submicron Pattern Generation by Oxidation of Polysilicon

This article discusses a method of generating submicron patterns on silicon wafers beyond the lithographic unit defined by optical or electron beam lithography. It is a well known fact that state-of-art lithography has the limit of a minimum feature size of 0.7 um for proximity corrected optics and 0.5 um for electron beams. The only way to make smaller line widths was the sidewall spacer technology which utilizes anisotropic etching characteristics of reactive ion etching. The spacer technology, however, generates only a positive pattern which resides near another lithographically defined lines. As a result, several more masking steps are necessary to break the closed patterns either in circles or rectangles. In this disclosure, a negative pattern with line width down to 0.1 um was successfully made. The steps of this technique are as follows: 1) Deposit nitride and polysilicon on a Si wafer with a thin stress relief oxide. 2) Make a pattern desired for submicron features. 3) Reactive ion etch the polysilicon layer.
4) Oxidize the poly Si. 5) Transfer the pattern on the polysilicon, now shrunk, to the nitride layer or to the silicon substrate. The thickness of polysilicon can be adjusted by considering optical minimum feature and final size after oxidation. Oxide growth on the polysilicon edges actually determines the final pattern opening width. Figs. 1 and 2 show a specific application that creates submi...