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Multisource Interrupt Vector Generation and Acknowledgement

IP.com Disclosure Number: IPCOM000061103D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Marshall, JR: AUTHOR

Abstract

A system is provided for identifying an interrupt, in a microprocessor system, in which a vector, representing the interrupt, includes the interrupt level and the interrupt states of all interrupt sources at that interrupt level. Thus, the microprocessor receives an interrupt input which includes the level of the interrupt so that the interrupt acknowledgement is directed to the appropriate level. This system minimizes both hardware and code time requirements. The present embodiment assumes a level sensitive microprocessor interrupt system of M levels (m1, m2, m3, etc.). The level identification is encoded within an interrupt vector of V bits. Due to hardware constraints, X (X > 0) vector bits must be in a predetermined state.

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Multisource Interrupt Vector Generation and Acknowledgement

A system is provided for identifying an interrupt, in a microprocessor system, in which a vector, representing the interrupt, includes the interrupt level and the interrupt states of all interrupt sources at that interrupt level. Thus, the microprocessor receives an interrupt input which includes the level of the interrupt so that the interrupt acknowledgement is directed to the appropriate level. This system minimizes both hardware and code time requirements. The present embodiment assumes a level sensitive microprocessor interrupt system of M levels (m1, m2, m3, etc.). The level identification is encoded within an interrupt vector of V bits. Due to hardware constraints, X (X > 0) vector bits must be in a predetermined state. Therefore, V > log2M+X and V-(log2M+X) = N vector bits that are available to indicate source status. Since each of the N bits indicates the status of a single source, n, it follows that up to N different sources are allowed at each level. Each source interrupt is associated with one level of interrupt m, where 1 < m < M. Fig. 1 shows the circuitry for one of the level m interrupt sources. It is seen that an interrupt condition on line 1 sets interrupt source latch 2. The latch output 3 is dot ORed 4 with all other level m source interrupt outputs, and line 5 goes to the microprocessor level m interrupt input. When the microprocessor acknowledges the level m interrupt, the acknowled...