Browse Prior Art Database

Correcting Detected Triple Bit Errors

IP.com Disclosure Number: IPCOM000061135D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Fabrizio, M: AUTHOR [+3]

Abstract

A machine employing an invert retry scheme to bypass double bit errors by correct either 1 or 2 of the bit, may also use this mechanism to increase system integrity and prevent machine failures caused by detectable triple bit errors.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Correcting Detected Triple Bit Errors

A machine employing an invert retry scheme to bypass double bit errors by correct either 1 or 2 of the bit, may also use this mechanism to increase system integrity and prevent machine failures caused by detectable triple bit errors.

Each bit of a 39 sec double error detection code has 3 of the 7 check bits for a weight. The correction stage uses three syndromes to correct the data bit. A multiple error could cause many syndromes which would correct the wrong bit/bits causing data integrity. The multiple (3) usually results in 5 syndromes which decode into more than one corrected bit. Using the existing correction logic for the 39-bit error, with some additi logic allows the invert retry to prevent system failure. The seven-way AND allows only a 3-syndrome situation to correct or invert a bit. Anything other than a legitimate single or an undetected triple would not cause a correction.

The ECC circuitry recognizes the odd syndrome count as a correctable error situation. An even syndrome count would be an uncorrectable error situation. The 7-way ANDs and 8-way ORs form a decision maker to determine if a bit was actually corrected. The odd syndromes plus the "bit not being corrected" indicator, indicate the possibility of a 3-bit error taking place. The 3-bit indicator sets off the invert retry that will take care of the down situation until fresh hardware relieves it.

Disclosed anonymously.

1