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Subcollector Anneal Argon Prepurge

IP.com Disclosure Number: IPCOM000061143D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Adamcek, ME: AUTHOR [+5]

Abstract

In the manufacture of semiconductors a subcollector annealing step in the process involves oxide growth at tempreatures of about 800oC with annealing taking place at 1100oC. While the procedures functioned satisfactorily when wafer load was placed in the annealing furnace, it was not possible to maintain sub- collector screen oxide thickness and sheet resistance uniformity when the wafer load was doubled. A procedure has been developed which utilizes an argon prepurge at the beginning of the subcol- letor anneal cycle to achieve temperature stabilization before the oxidation step begins.

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Subcollector Anneal Argon Prepurge

In the manufacture of semiconductors a subcollector annealing step in the process involves oxide growth at tempreatures of about 800oC with annealing taking place at 1100oC. While the procedures functioned satisfactorily when wafer load was placed in the annealing furnace, it was not possible to maintain sub- collector screen oxide thickness and sheet resistance uniformity when the wafer load was doubled. A procedure has been developed which utilizes an argon prepurge at the beginning of the subcol- letor anneal cycle to achieve temperature stabilization before the oxidation step begins.

In the present process the layer wafer load is held at about 800oC in an argon atmosphere for several minutes. A thermal equilibrium is reached and oxygen is then introduced to grow the oxide. The thermal stabilization achieved provides a more uniform oxide and resistivity growth which leads to better surface resistivity (RS). This method eliminates the oxide and resistivity uniformity problems which existed when oxide growth time was extended with increased furnace loads.

The prepurge step permits a substantial increase in product capacity per anneal tube. Wafers annealed by this method have shown at least equivalency in terms of surface resistivity oxide measurements and leakage-limited yield as compared to the wafer anneal process previously used.

Disclosed anonymously.

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