Browse Prior Art Database

Very Fast Fundamental Mode Lssd Compatible Divider

IP.com Disclosure Number: IPCOM000061156D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Cahill, JJ: AUTHOR

Abstract

This is a method of achieving LSSD (level-sensitive scan design) compatibility in a state machine whose feedback path contains only one logic block. The state machine can then be tested by LSSD methods.

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Very Fast Fundamental Mode Lssd Compatible Divider

This is a method of achieving LSSD (level-sensitive scan design) compatibility in a state machine whose feedback path contains only one logic block. The state machine can then be tested by LSSD methods.

The method of designing very fast LSSD compatible fundamental mode circuits will be illustrated by the divide-by-two cir shown in the figure. This circuit is implemented in a NAND-based technology that allows 'wired-AND' connections. The characteristics of this divide-by-two circuit are shown by the timing diagram and the state equations below. Timing: OSC, X, Y State Equations: These will take the form of: next state = f(present state, clock)

The state machine is composed of blocks 1 through 8 in the figure 1. The state machine outputs labelled X, X-, Y, and Y- are each determined independently to insure that they are available only one block delay after the state machine is clocked by the signals labelled OSC and OSC--- .

The LSSD latches are labelled SRL 1 through 4. The feedback path of the LSSD latch (blocks 9 and 10) is not part of the feedback path of the state machine. The LSSD latch is placed alongside the state machine in such a way as to control the inputs of the state machine but not be present in the feedback path of the state machine.

Circuits designed using the methods of this disclosure will have two operating modes. The first is the functional mode where the signals OSC and OSC--- are used to step...