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Improved Dibit (2,8) Code

IP.com Disclosure Number: IPCOM000061179D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Howell, TD: AUTHOR [+3]

Abstract

In the dibit (2,8) code, single transitions and dibits, which comprising a pair of transitions, each representing the symbol "l", are encoded so that at least two, and at most eight, symbols "0" occur between any pair of dibits and/or single transitions. However, in previous dibit encoders, as described in [1], there is no restriction on the number of consecutive dibits separated by the minimum number of symbols "0". Without a constraint on the number of consecutive dibits separated by the minimum number of symbols "0", error propagation in the detector is not controllable. In the proposed code, error propagation in the detector is limited by allowing no more than two consecutive combinations of dibits separated by the minimum of two symbols "0".

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Improved Dibit (2,8) Code

In the dibit (2,8) code, single transitions and dibits, which comprising a pair of transitions, each representing the symbol "l", are encoded so that at least two, and at most eight, symbols "0" occur between any pair of dibits and/or single transitions. However, in previous dibit encoders, as described in [1], there is no restriction on the number of consecutive dibits separated by the minimum number of symbols "0". Without a constraint on the number of consecutive dibits separated by the minimum number of symbols "0", error propagation in the detector is not controllable. In the proposed code, error propagation in the detector is limited by allowing no more than two consecutive combinations of dibits separated by the minimum of two symbols "0". Thus, any preceding or following dibit is separated by at least three symbols "0". In this newly constrained code, error propagation in the detection of the dibits is eliminated. Error propagation in the decoder is limited to a maximum of eight information bits. Transitions in prior art dibit encoders, as described in [2] occur every 2.5 clock periods. In the proposed code, all transitions other than those comprising a dibit are at least three clock periods away from a preceding or following transition. Encoder logic equations and table are given in Figs. 1 and 2, respectively. Decoder logic equations and table are given in Figs. 3 and 4, respectively. References [1] R. L. Adler, M. Hassner, B....