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Browse Prior Art Database

Physical Channel Architecture

IP.com Disclosure Number: IPCOM000061185D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR

Abstract

A multi-bus high performance system is described that can be packaged within the pin constraints of a Solid Logic Technology (SLT) board and that is capable of unimpeded communication between (a) CPU and cache, (b) cache and storage, and (c) I/O and storage. This allows the system to be packaged on standard circuit cards plugged into an SLT board. A Card-On-Board arrangement suitable for the system is shown in Fig. 1. The CPU is divided between two cards. A division is tentatively, but not necessarily, made between the processor and the storage controller sections. Connections between these cards are made through normal board wiring. The communication path between main storage and the storage controller is made via the top card connectors on the storage controller card and each main storage expansion card.

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Physical Channel Architecture

A multi-bus high performance system is described that can be packaged within the pin constraints of a Solid Logic Technology (SLT) board and that is capable of unimpeded communication between (a) CPU and cache, (b) cache and storage, and (c) I/O and storage. This allows the system to be packaged on standard circuit cards plugged into an SLT board. A Card-On-Board arrangement suitable for the system is shown in Fig. 1. The CPU is divided between two cards. A division is tentatively, but not necessarily, made between the processor and the storage controller sections. Connections between these cards are made through normal board wiring. The communication path between main storage and the storage controller is made via the top card connectors on the storage controller card and each main storage expansion card. These connections are made with rigid SLT crossover assemblies. Three crossovers are necessary, which leaves one top card socket available as a spare on each of these cards. A total of 63 signal lines are required on this interface. These lines are referred to as the storage controller bus and are as follows: The channel bus is primarily driven from a storage expansion card. The particular storage expansion card is chosen by comparing the appropriate address bits with its particular position in the card file. The chosen card can then complete a cycle steal transfer. A total of 65 signal lines are required for a cycle steal transfer. These lines are referred to as the storage channel bus and are as follows: An additional subset of the channel bus is referred to as the channel command bus. This bus consists of channel directed signals which cannot conveniently communicate with a main storage expansion card. Twelve signals are identified for this bus. Four of these signals also communicate with the storage expansion cards. The lines are as follows:

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