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Data Detector and Clock Recovery Circuit for Dibit (2,8) Code

IP.com Disclosure Number: IPCOM000061189D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Howell, TD: AUTHOR [+4]

Abstract

A detector for the dibit (2,8) code, having at least three clock cycles between transitions (other than those comprising dibits) and constraints on runs of closely spaced dibits, is described. The constraints on runs of closely spaced dibits in the (2,8) code are described on pages 507-509. To reproduce input data, the proposed data detector uses the characteristics which distinguish dibits (i.e., transitions written in adjacent clock cells) from all other data patterns. The dibit readback signal will be smaller than the readback signal for all other code patterns, and will be shifted with respect to clock periods.

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Data Detector and Clock Recovery Circuit for Dibit (2,8) Code

A detector for the dibit (2,8) code, having at least three clock cycles between transitions (other than those comprising dibits) and constraints on runs of closely spaced dibits, is described. The constraints on runs of closely spaced dibits in the (2,8) code are described on pages 507-509. To reproduce input data, the proposed data detector uses the characteristics which distinguish dibits (i.e., transitions written in adjacent clock cells) from all other data patterns. The dibit readback signal will be smaller than the readback signal for all other code patterns, and will be shifted with respect to clock periods. For the proposed code, the leading peak of a dibit readback signal could be pushed forward in time as much as one-half clock period and the trailing peak may be pushed backward in time approximately the same amount. The detector comprises a delay line differentiator, a pair of phase detector/data standardizers and a correction circuit. A control signal (SH) for steering data represented by dibits through one of the phase detector/data standardizers and for steering data represented by ordinary readback signals through the other phase detector/data standardizer, is derived from input data. Each of the phase detector/data standardizers is similar to conventional designs but modified to shorten the allowable time between input pulses from the data detector. In addition, the circuit is synchronous, not requiring "single-shot" adjustment. The correction circuit produces standardized output data in response to signals received from the two data standardizers. It watches for a "1 0 1" pattern, characteristic of a dibit. When such a pattern is detected, the ordinary data stream is corrected to indicate a dibit by replacing the current bits with the pattern "0 1 1 0". Referring now to Fig. 1, data is detected from the content of a readback signal applied to the input of amplifier 11. Delay line 12 and comparator 13 detect peaks in the output of amplifier 11. The output of comparator 13 is a pulse having a leading edge selectably delayed beyond the occurrence of a peak in the readback signal. Comparators 14A, 14B and OR gate 15 discriminate the amplitude of a single transition from a dibit. The output of OR gate 15 is control signal SH, which is high whenever the ampl...