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Code Coverage Mapper With Branch Analysis for an Intel 8088 Micro-Processor in Maximum Mode

IP.com Disclosure Number: IPCOM000061192D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Bowles, DJ: AUTHOR [+4]

Abstract

A code coverage mapper ascertains the instructions that have not been executed and the conditional branch instructions that have not been executed both ways when an Intel 8088 microprocessor is in maximum mode. When testing software to insure that it is functioning according to its specification, it is desirable to know whether the test cases produced actually execute all of the code and all of the conditional branches both ways. If not, new test cases must be developed to force the paths not taken. When an Intel 8088 microprocessor 1 fetches an instruction, the address of the instruction fetched is queued in a prefetch queue block 2, which consists of five 74LS224 FIFO (first-in, first out) memories. These memories are controlled by decoding status lines of the Intel 8088 microprocessor 1 in a decode and logic block 3.

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Code Coverage Mapper With Branch Analysis for an Intel 8088 Micro- Processor in Maximum Mode

A code coverage mapper ascertains the instructions that have not been executed and the conditional branch instructions that have not been executed both ways when an Intel 8088 microprocessor is in maximum mode. When testing software to insure that it is functioning according to its specification, it is desirable to know whether the test cases produced actually execute all of the code and all of the conditional branches both ways. If not, new test cases must be developed to force the paths not taken. When an Intel 8088 microprocessor 1 fetches an instruction, the address of the instruction fetched is queued in a prefetch queue block 2, which consists of five 74LS224 FIFO (first-in, first out) memories. These memories are controlled by decoding status lines of the Intel 8088 microprocessor 1 in a decode and logic block 3. When addresses are to be executed sequentially, a Read Queue signal is supplied from block 3 to the prefetch queue block 2 and to a branch analysis latch 4. If non-sequential execution of the addresses is to occur, then a Clear Queue signal is supplied from the block 3 to the prefetch queue block 2. The branch analysis latch 4 retains the address of an instruction executed by the Intel 8088 microprocessor for one additional instruction execution cycle. In this additional cycle, a logic block 7 determines whether the next instruction byte executed came from the address immediately following the address in the branch analysis latch 4...