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Module Chipsite Partial EC Capability

IP.com Disclosure Number: IPCOM000061195D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Balderes, D: AUTHOR [+3]

Abstract

This technique provides increased chip and circuit density on a given module substrate size without the potential scrap and long turnaround time for a replacement change associated with a zero engineering change (EC) capability design. Current multichip packages employ full EC capability designs which require large surface areas devoted to EC pads and routing tracks for discrete wire utilized to change logical function or wire routing. This large area requirement reduces the potential chip capacity of a given substrate size and thereby lowers the circuit density of the package. The decrease in circuit density is reflected in longer wiring paths and therefore lower performance of the packaged electronics. A potential solution to this problem is the elimination of the EC capability and the area associated with the EC function.

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Module Chipsite Partial EC Capability

This technique provides increased chip and circuit density on a given module substrate size without the potential scrap and long turnaround time for a replacement change associated with a zero engineering change (EC) capability design. Current multichip packages employ full EC capability designs which require large surface areas devoted to EC pads and routing tracks for discrete wire utilized to change logical function or wire routing. This large area requirement reduces the potential chip capacity of a given substrate size and thereby lowers the circuit density of the package. The decrease in circuit density is reflected in longer wiring paths and therefore lower performance of the packaged electronics. A potential solution to this problem is the elimination of the EC capability and the area associated with the EC function. The drawback to such a scheme is debug time and field change activity is both long in duration and causes large amounts of scrapped hardware. The technique described allows EC capability to be performed on a portion of the total number of I/O connections to the chip package without employing EC pads for every I/O. The technique allows one to personalize the EC wiring to connect to any of the chip I/O. The only limitation is the number of EC pads created in the initial design for wire bonding. The net result is a greatly reduced area required for EC pads and wiring tracks. Therefore, an increase is achieve...