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Phase-Locked Oscillator Charge Pump

IP.com Disclosure Number: IPCOM000061197D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Chapman, DB: AUTHOR [+2]

Abstract

In a direct-access storage device, the function of a phase-locked oscillator (PLO) is to provide a system clock that is phase-locked to data which has been read from recording media or that is phase-locked to the servo clock during write mode. The PLO also standardizes readback data to reject jitter due to bit shift, and provide fast synchronization to read data. The present PLO configuration, shown in Fig. 1, consists of a voltage-controlled oscillator (VCO), a filter network, and an error detector comprising phase discriminator and charge pump circuitry. The filter is a lead/lag network for compensation. The PLO has a run mode and a fast sync mode.

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Phase-Locked Oscillator Charge Pump

In a direct-access storage device, the function of a phase-locked oscillator (PLO) is to provide a system clock that is phase-locked to data which has been read from recording media or that is phase-locked to the servo clock during write mode. The PLO also standardizes readback data to reject jitter due to bit shift, and provide fast synchronization to read data. The present PLO configuration, shown in Fig. 1, consists of a voltage-controlled oscillator (VCO), a filter network, and an error detector comprising phase discriminator and charge pump circuitry. The filter is a lead/lag network for compensation. The PLO has a run mode and a fast sync mode. In run mode, the PLO is locked to read data to provide standardized data, or to the servo clock for writing data to the media, and is designed for low gain and low bandwidth while operating in this mode. In fast sync mode, the PLO achieves frequency and phase alignment to read data, or to the servo clock, and is designed for high gain and high bandwidth while operating in this mode. If the bandwidth/gain of the PLO is not increased for fast sync mode operation over that required for run mode, fast synchronization capability is limited. One way to increase PLO bandwidth/gain is to increase charge pump current. However, if only one steering diode is used, the charge pump operates at different current values having different response characteristics and a circuit phase error is present between fast sync mode and run mode. The steady-state phase error caused by the charge pump circuit between run mode and fast sync mode must be corrected to achieve phase lock when switching modes. Such phase error caused by switching from one mode to the other is reduced in this circuit by using separate steering diode networks, clamp networks, increase current sources and decrease current sources for each mode. In the charge pump concept shown in Fig. 2, only one charge pump is ope...