Browse Prior Art Database

Partial Result Duplication

IP.com Disclosure Number: IPCOM000061201D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR

Abstract

In some processors, the data flow including General Purpose Registers (GPRs), Arithmetic Logic Unit (ALU), System Registers, etc., are byte sliced to eliminate as many chip boundary crossings as possible. This is due to driver/receiver delays being considerably greater than internal logic gate delays. In a representative byte slice processor, only shifted data or carries (internal in the ALU) must cross chip boundaries. Typically, only a limited set of instructions both shift data and require an arithmetic function to be performed on this data, such as Multiply First Step (MFS), Multiply Step (MPS), Divide Step (DVS), and Shift Left One then Add (SLOA). Therefore, all other instructions have only one-chip boundary crossing in the worst-case dataflow path.

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Partial Result Duplication

In some processors, the data flow including General Purpose Registers (GPRs), Arithmetic Logic Unit (ALU), System Registers, etc., are byte sliced to eliminate as many chip boundary crossings as possible. This is due to driver/receiver delays being considerably greater than internal logic gate delays. In a representative byte slice processor, only shifted data or carries (internal in the ALU) must cross chip boundaries. Typically, only a limited set of instructions both shift data and require an arithmetic function to be performed on this data, such as Multiply First Step (MFS), Multiply Step (MPS), Divide Step (DVS), and Shift Left One then Add (SLOA). Therefore, all other instructions have only one- chip boundary crossing in the worst-case dataflow path. However, all of these instructions requiring both a shift and ALU function only require a shift left one. By duplicating the high-order bit or each byte in the next high-order chip, a shift left one can be done with no chip crossing. This means the cycle time can be significantly reduced to increase the CPU performance. The drawing shows the data paths required in a byte slice processor for instructions which require both a shift and an ALU function. The high-order bits of bytes 1, 2, 3 (represented as W, X, Y, respectively) are duplicated in bytes 0, 1 and 2. Since bits W, X, and Y are copied in both chips, the only drivers (D) and receivers (R) in the data path are for the ALU carri...