Browse Prior Art Database

Optimal Memory Organization, Arbitration Scheme and Addressing Scheme for a High Resolution Bit-Mapped Display

IP.com Disclosure Number: IPCOM000061218D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Ko, MA: AUTHOR [+2]

Abstract

In a high resolution bit-mapped display which includes a control system having a data bus n bits wide, a bit map dynamic memory in communication with the system and a display adapter providing serial data output for display on a raster scanning device such as a CRT, a memory organization, memory access arbitration scheme and an addressing scheme for the memory are provided which increase the effective memory bandwidth and eliminate the need for additional refresh cycles to refresh the dynamic memory. The system includes three aspects. First, the memory is organized such that the width of the data path to the display adapter is equal to a multiple of the width of the system data bus. This allows the display refresh-related access to fetch more data per memory access, thereby freeing up extra bandwidth for the system.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Optimal Memory Organization, Arbitration Scheme and Addressing Scheme for a High Resolution Bit-Mapped Display

In a high resolution bit-mapped display which includes a control system having a data bus n bits wide, a bit map dynamic memory in communication with the system and a display adapter providing serial data output for display on a raster scanning device such as a CRT, a memory organization, memory access arbitration scheme and an addressing scheme for the memory are provided which increase the effective memory bandwidth and eliminate the need for additional refresh cycles to refresh the dynamic memory. The system includes three aspects. First, the memory is organized such that the width of the data path to the display adapter is equal to a multiple of the width of the system data bus. This allows the display refresh-related access to fetch more data per memory access, thereby freeing up extra bandwidth for the system. Second, access to the memory is arbitrated by allocating a portion of the display adapter access cycle for memory access by the display adapter long enough to complete one access to the memory and by polling the system controller one or more times during the balance of the access cycle, subject to the constraint that the occurrence of a poll of the system controller must occur early enough in the cycle to assure completion of the system memory access before the end of the access cycle time. Third, refresh of the memory is assured by selecting horizontal and vertical counter values from the system controller that occur within the refresh time limit in all possible modes of operation as row addresses for the dynamic memory. Preferred implementations utilize 8- or 16-bit system buses with a display adapter data path to the memory 64 bits wide. The memory is organized using sixteen 16K by 4-bit modules for a total of 16K by 64 bits. The display adapter includes a shift register which receives the 64 output bits from the memory in parallel and shifts the bits out serially to be supplied to the raster scanner. The system bus communicates with the memory by multiplexing desired bytes into the system bus. In commercially available RAMs, the memory access cycle time is about 260 nanoseconds. As implemented, the display adapter is allocated 300 nanoseconds to access the memory. Therefore, in the time required for the display to traverse 64 pels (960 nanoseconds in a typical display), the display adapter needs to have access to the memory for 300 nanoseconds. The remaining 660 nanoseconds are reserved for the system controller. The display adapter will always use its allocated time slot. The me...