Browse Prior Art Database

Improved Channel Length Control

IP.com Disclosure Number: IPCOM000061219D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+2]

Abstract

To improve channel length control in insulated gate field-effect transistors (IGFETs), a photoresist mask used for subsequent etch definition of the gate electrode is also used as an implant mask for source and drain implants through the polysilicon film. Thus, etching tolerances are no longer a factor in channel length control. Referring to Fig. 1, a layer of silicon dioxide 6 is grown on a silicon substrate 8, and a layer of polysilicon 4 is formed on oxide 6. A layer of photoresist is deposited on polysilicon 4, and is exposed and developed to define masking image 2 which defines the gate electrode to be subsequently formed by etching the polysilicon layer 4. Prior to etching the polysilicon 4, source 10 and drain 12 regions are formed by implanting the appropriate species through unmasked portions of the polysilicon 4.

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Improved Channel Length Control

To improve channel length control in insulated gate field-effect transistors (IGFETs), a photoresist mask used for subsequent etch definition of the gate electrode is also used as an implant mask for source and drain implants through the polysilicon film. Thus, etching tolerances are no longer a factor in channel length control. Referring to Fig. 1, a layer of silicon dioxide 6 is grown on a silicon substrate 8, and a layer of polysilicon 4 is formed on oxide 6. A layer of photoresist is deposited on polysilicon 4, and is exposed and developed to define masking image 2 which defines the gate electrode to be subsequently formed by etching the polysilicon layer 4. Prior to etching the polysilicon 4, source 10 and drain 12 regions are formed by implanting the appropriate species through unmasked portions of the polysilicon 4. Thus, the mask image 2 defines channel length L between regions 10 and 12. The polysilicon 4 is then dry etched to result in the structure shown in Fig. 2. Standard processing is used to complete the device and circuit structure.

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