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Data Bypass Methodology for a Performance Pipeline Processor

IP.com Disclosure Number: IPCOM000061222D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+4]

Abstract

Efficient utilization of arithmetic logic unit (ALU)-generated data in a pipeline processor is maintained when the target register is also the source of the next instruction. A central processing unit (CPU) may be designed as a pipeline processor. Such a processor may be organized so that while the result of instruction #1 is being stored away in the general-purpose registers (GPR write cycle), instruction #2 is being executed in the ALU (Execute cycle), the data associated with instruction #3 is being accessed from the general-purpose registers (GPR read cycle), and instruction #4 is being accessed from main storage (Fetch cycle).

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Data Bypass Methodology for a Performance Pipeline Processor

Efficient utilization of arithmetic logic unit (ALU)-generated data in a pipeline processor is maintained when the target register is also the source of the next instruction. A central processing unit (CPU) may be designed as a pipeline processor. Such a processor may be organized so that while the result of instruction #1 is being stored away in the general-purpose registers (GPR write cycle), instruction #2 is being executed in the ALU (Execute cycle), the data associated with instruction #3 is being accessed from the general-purpose registers (GPR read cycle), and instruction #4 is being accessed from main storage (Fetch cycle). Since all four individual cycles are executing concurrently, the net effect for performance purposes is to process sequential instructions at a rate of one instruction per machine cycle, instead of the four cycles that the instruction actually takes. A problem occurs when the results of one instruction is destined to be stored in a target register (RT) that is also a source register (RS) of the next sequential instruction. The solution, as shown in Fig. 1, is to provide a feedback path from the output of the ALU 1 to the input multiplexers 2 and 3 of the P and G registers 4 and 5 which drive the ALU. This path is represented by a darker line in Fig. 1. If RT equals the next sequential RS, the appropriate multiplexers are conditioned to allow the ALU-generated data to be used...