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High Speed Shift Mechanism

IP.com Disclosure Number: IPCOM000061225D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR

Abstract

A barrel shifter is incorporated in a CPU as an inherent part of the ALU without affecting the cycle time of the machine. Fig. 1 is a simplified block diagram showing the possible locations that a barrel shifter would normally be incorporated into the data flow path associated with an ALU. As can be seen, all normally used locations require that the data flows through the ALU and the barrel shifter in a sequential fashion. This results in a longer total data path length and, consequentially, a longer machine cycle time. The barrel shifter, described here, performs its function without affecting the length of the total data path.

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High Speed Shift Mechanism

A barrel shifter is incorporated in a CPU as an inherent part of the ALU without affecting the cycle time of the machine. Fig. 1 is a simplified block diagram showing the possible locations that a barrel shifter would normally be incorporated into the data flow path associated with an ALU. As can be seen, all normally used locations require that the data flows through the ALU and the barrel shifter in a sequential fashion. This results in a longer total data path length and, consequentially, a longer machine cycle time. The barrel shifter, described here, performs its function without affecting the length of the total data path. This is accomplished by taking advantage of the fact that in most system architectures there are usually no commands which require that data shifted more than one position be arithmetically manipulated. It may, of course, be logically manipulated. In other words, if it is necessary to add or subtract a quantity to a data operand, then the number of positions that operand may be shifted is usually limited to 1 or 0 (left). Here, the input data multiplexers to the ALU are designed with a shift left 1 capability and still meet the fan-in/fan-out restrictions of the logic family. This allows the ALU to accomplish a shift left 1 and add or subtract in one cycle with no increase in cycle time. Fig. 2 is a block diagram of an implementation for a 32-bit barrel shifter. The input data multiplexers 1 and 2 (B mux, A mux)...