Browse Prior Art Database

Pulsed ECL Decoder

IP.com Disclosure Number: IPCOM000061227D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Wernicke, FC: AUTHOR [+2]

Abstract

While conventional emitter-coupled logic (ECL) decoders are very fast, their power consumption becomes prohibitive when considered for use with denser designs, such as large clocked arrays. The pulsed ECL decoder scheme here described proves very effective in reducing ECL decoder power in such applications at only a slight delay penalty. Fig. 1 shows an ECL decoding scheme for an 8 T 256 decode application. Pulsing circuits are shown in Figs. 2 and 3. ECL decoder power reduction is achieved in this manner: 1) Each true/complement (T/C) generator and word driver current are clocked. 2) A speed-up capacitor is added to each decoder circuit. 3) Decoder circuit resistor values are increased. Referring to Figs. 2 and 3: During Standby, all outputs of the T/C generators are held low.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 63% of the total text.

Page 1 of 2

Pulsed ECL Decoder

While conventional emitter-coupled logic (ECL) decoders are very fast, their power consumption becomes prohibitive when considered for use with denser designs, such as large clocked arrays. The pulsed ECL decoder scheme here described proves very effective in reducing ECL decoder power in such applications at only a slight delay penalty. Fig. 1 shows an ECL decoding scheme for an 8 T 256 decode application. Pulsing circuits are shown in Figs. 2 and 3. ECL decoder power reduction is achieved in this manner: 1) Each true/complement (T/C) generator and word driver current are clocked. 2) A speed-up capacitor is added to each decoder circuit. 3) Decoder circuit resistor values are increased. Referring to Figs. 2 and 3: During Standby, all outputs of the T/C generators are held low. This is accomplished by providing two separate current sinks for each T/C generator. The extra current sink is controllable by the clock and is employed to pull down the high output during Standby. For Access, the extra current sink is turned-off first, so that all unselected decoders are discharged. With the speed-up capacitor C, the high node of the decoder output can be quickly discharged even though a small DC turn-on current is used, e.g., ~ 0.1 ma. To prevent erroneous word line (W/L) selection, the W/L is pulled down only after all of the unselected decoders are discharged. This is controlled by a delayed clock A (Fig. 2) through the power switch transistor 1. Thu...