Browse Prior Art Database

Control Sequencer Building Block

IP.com Disclosure Number: IPCOM000061232D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Rodriguez, JR: AUTHOR [+2]

Abstract

A technique is described whereby the control sequencer described can be used as the basic building block in a regular array structure. Two features have been incorporated to make the sequencer structure practical for use as a basic building block. 1. A logic AND/OR array is programmable and can be personalized for a given sequential machine description. Translation from high level design notation to actual hardware is easily implemented. 2. The number of AND gates in the logic array is reduced. The resulting design is synchronous and free of races. The basic control sequencer structure (Fig. 1) shows the AND/OR array 10 of the sequencer that implements the control sequence of the flow chart in Fig. 2.

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Control Sequencer Building Block

A technique is described whereby the control sequencer described can be used as the basic building block in a regular array structure. Two features have been incorporated to make the sequencer structure practical for use as a basic building block. 1. A logic AND/OR array is programmable and can be personalized for a given sequential machine description. Translation from high level design notation to actual hardware is easily implemented. 2. The number of AND gates in the logic array is reduced. The resulting design is synchronous and free of races. The basic control sequencer structure (Fig. 1) shows the AND/OR array 10 of the sequencer that implements the control sequence of the flow chart in Fig. 2. OR gate 11 enables multiplexer 20 at the input of the state storage element 30, so that the next state function is performed by recycling the contents of state storage element 30 (present state) into itself through the multiplexer 20 on the next transition of clock 40 (next state time). Therefore, non- state transitions need not be defined in the AND/OR array, thereby reducing the amount of logic required. Figs. 3a-3d show the hardware implementation of flow chart logic. This control sequencer array structure may be replicated, expanded, reduced or modified for use within a regular array structure according to the design function required.

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