Browse Prior Art Database

Store/Write Structure for Static Rams

IP.com Disclosure Number: IPCOM000061240D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR [+2]

Abstract

A technique is described for improving the performance of a memory array chip by providing the means for storing single through block stores for static RAMs (random-access memories) without requiring a preceding fetch ("prefetch") cycle. A static RAM chip is presently required in high performance memory array applications to satisfy performance requirements. For such applications, the static RAM chip must have similar functional characteristics to those of a dynamic RAM, namely a "page-mode-like" transfer mechanism of more than one data transfer from the array chip. Fig. 1 illustrates a basic functional block diagram for such a RAM chip, including the structure for avoiding "prefetch" for partial stores. Elements 9, 10, 11 and 15 in Fig. 1 are the principal on-chip additions necessary to implement this scheme. Fig.

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Store/Write Structure for Static Rams

A technique is described for improving the performance of a memory array chip by providing the means for storing single through block stores for static RAMs (random-access memories) without requiring a preceding fetch ("prefetch") cycle. A static RAM chip is presently required in high performance memory array applications to satisfy performance requirements. For such applications, the static RAM chip must have similar functional characteristics to those of a dynamic RAM, namely a "page-mode-like" transfer mechanism of more than one data transfer from the array chip. Fig. 1 illustrates a basic functional block diagram for such a RAM chip, including the structure for avoiding "prefetch" for partial stores. Elements 9, 10, 11 and 15 in Fig. 1 are the principal on-chip additions necessary to implement this scheme. Fig. 2 expands on the block diagram of Fig. 1, depicting a logical structure for those elements previously associated with the disclosed technique and the controls used for its operation. The logical function and interaction of the mask and data store registers for storage into the memory array data buses through D0 and D1 are shown. Also shown is a fetch path into and out of the register configuration, to be consistent with the block function diagram of Fig. 1. Figs. 3 and 4 describe the functional operation of the chip structure for Read and Write operations. During the Write or Store operation, both data and the numb...