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RAS Characteristics of Hierarchical Multilevel Array Design

IP.com Disclosure Number: IPCOM000061251D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Bennington, FE: AUTHOR [+3]

Abstract

A technique is described whereby reliability, availability and serviceability (RAS) characteristics of hierarchical multilevel array systems are designed to reduce the complexity of error checking by using a distributed function testing approach and to provide additional error detection function to the system by providing a certain amount of redundancy between the diagnostic machine states and the major states of the interface. Multiple levels of error detection and reporting are used. At each level of control, there are algorithm state machines (ASM). Each sequencer has an encoded set of lines that determine what state a particular machine is in at any time. An example contains four levels and their control functions, as shown in the organization flow diagram (Fig.

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RAS Characteristics of Hierarchical Multilevel Array Design

A technique is described whereby reliability, availability and serviceability (RAS) characteristics of hierarchical multilevel array systems are designed to reduce the complexity of error checking by using a distributed function testing approach and to provide additional error detection function to the system by providing a certain amount of redundancy between the diagnostic machine states and the major states of the interface. Multiple levels of error detection and reporting are used. At each level of control, there are algorithm state machines (ASM). Each sequencer has an encoded set of lines that determine what state a particular machine is in at any time. An example contains four levels and their control functions, as shown in the organization flow diagram (Fig. 1) as follows: Level 0 - Parity checking - Parity errors on interrupt. Data flow hardware detects a parity error when I/O interrupt parameters are passed from the device. Service gate return and address gate return are active immediately, i.e., hardware detectable errors. Level 1 - Bus operations - Service gate time-out and Poll time-out. No device response, service gate return and pool return within 19 ms of processor- initiated service gate, i.e., bus time-outs. Level 2 - IPL and Supervisor function - Instruction time-out. Level 3 - Diagnostic Processor - Error reporting, set interface request and detect lower level error condition, i.e., h...