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Complementary Emitter-Coupled Logic to Open Collector Driver Circuit

IP.com Disclosure Number: IPCOM000061262D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Kroesen, RJ: AUTHOR [+3]

Abstract

This article describes the design of a complementary emitter-coupled logic (CECL) to off-chip open collector driver circuit which functions with a relatively small delay with neither PNP transistors or reference voltages. By means of the diode chains T2A-T4A and T2B-T4B shown in the above VTL open collector driver circuit, the input signal levels at (IN) and (NIN), nominally 5.0 and 4.7 volts, respectively, are stepped down to 1.8 and 1.5 volts, thereby saving power and improving circuit performance. The diode chains track, while accepting power supply variations of +/- 10% and temperature variations from 10ŒC to 100ŒC while maintaining a 300-millivolt differential at nodes T1 and T2. Transistors T2, TB1 and TC1 are employed to amplify the voltage swing from 300 millivolts to approximately 3.0 volts.

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Complementary Emitter-Coupled Logic to Open Collector Driver Circuit

This article describes the design of a complementary emitter-coupled logic (CECL) to off-chip open collector driver circuit which functions with a relatively small delay with neither PNP transistors or reference voltages. By means of the diode chains T2A-T4A and T2B-T4B shown in the above VTL open collector driver circuit, the input signal levels at (IN) and (NIN), nominally 5.0 and 4.7 volts, respectively, are stepped down to 1.8 and 1.5 volts, thereby saving power and improving circuit performance. The diode chains track, while accepting power supply variations of +/- 10% and temperature variations from 10OEC to 100OEC while maintaining a 300-millivolt differential at nodes T1 and T2. Transistors T2, TB1 and TC1 are employed to amplify the voltage swing from 300 millivolts to approximately 3.0 volts. TC1A is used to put the driver in a high Z mode. The dv/dt is controlled by using transistor TC1B as a CCS (capacitance collector to substrate) device and RC1 and RC2 in series with each other. The nominal dv/dt is 0.68 volt/nsec. Under worst-case conditions dv/dt is 1.0 volt/nsec. Nominal delay for this driver is 6.5 nsec.

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