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Using the Exponent ALU As an Extension to the Mantissa ALU for Bcd-To-Binary and Binary-To-Bcd Conversion in Floating Point

IP.com Disclosure Number: IPCOM000061266D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR [+2]

Abstract

This article describes an arrangement wherein the amount of logic required to implement in binary-coded decimal (BCD)-to-binary and binary-to-BCD conversions is reduced without a performance penalty in floating-point arithmetic by concatenating the exponent and mantissa ALUs (arithmetic and logic units). When two separate floating-point processors are implemented in a single silicon gate process (SGP) chip, maximum efficient utilization of chip area is necessary. In order to perform a BCD-to-binary or a binary-to-BCD conversion, a 76-bit ALU is required. The floating point processor, however, only has a 16-bit exponent ALU (EALU) and a 68-bit mantissa ALU (MALU).

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Using the Exponent ALU As an Extension to the Mantissa ALU for Bcd-To- Binary and Binary-To-Bcd Conversion in Floating Point

This article describes an arrangement wherein the amount of logic required to implement in binary-coded decimal (BCD)-to-binary and binary-to-BCD conversions is reduced without a performance penalty in floating-point arithmetic by concatenating the exponent and mantissa ALUs (arithmetic and logic units). When two separate floating-point processors are implemented in a single silicon gate process (SGP) chip, maximum efficient utilization of chip area is necessary. In order to perform a BCD-to-binary or a binary-to-BCD conversion, a 76-bit ALU is required. The floating point processor, however, only has a 16-bit exponent ALU (EALU) and a 68-bit mantissa ALU (MALU). Instead of increasing the width of either ALU to 76 bits, costing valuable chip area, the two ALUs are concatenated together with only two wires, using the 16 bits of the EALU and 60 bits of the MALU. This technique realizes a 76-bit-wide ALU at significant chip area savings. The present floating point processor is illustrated in the block diagram of the drawing and utilizes a commonly used algorithm to implement BCD-to-binary and binary-to-BCD conversion. This algorithm involves a series of shift right one bit followed by a subtract three from each group of four bits which are greater than or equal to 8, for BCD-to-binary conversion. For binary-to-BCD conversion, the procedure is...