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Memory Cell Arrangement With Common Read-Write Couplings

IP.com Disclosure Number: IPCOM000061271D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

This article concerns a memory cell arrangement in which a four-device cell can be arranged to function as a six-device cell in order to obtain improved performance and reduced pinch-off during access without serious increase in cell area. A basic static memory cell arrangement consists of six devices, i.e., two load devices, two cross-coupled transistor flip-flops, and two I/O devices for read-write. Four-device cells are generally smaller but slower than six-device cells but with the cell arrangement to be described, a four-device cell will behave as a six-device cell during access, with consequent gain in performance and little loss in density. In Fig.

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Memory Cell Arrangement With Common Read-Write Couplings

This article concerns a memory cell arrangement in which a four-device cell can be arranged to function as a six-device cell in order to obtain improved performance and reduced pinch-off during access without serious increase in cell area. A basic static memory cell arrangement consists of six devices, i.e., two load devices, two cross-coupled transistor flip-flops, and two I/O devices for read- write. Four-device cells are generally smaller but slower than six-device cells but with the cell arrangement to be described, a four-device cell will behave as a six- device cell during access, with consequent gain in performance and little loss in density. In Fig. 1, the two I/O devices for read-write are shown as shared between a number of memory cells, the four remaining devices thereby doing the work of the six usually found in more conventional memory cell arrangements. Fig. 2 illustrates the application of the disclosed approach to a split emitter merged-transistor logic (SEMTL) arrangement with common read-write devices. The array in both figures consists of 256 rows x 160 columns if M = 16, N = 16 and L = 160. In Fig. 1, the NPN transistor is assumed to be poly-based and to have polysilicide emitters. Bit segments are the N+ silicide connections, and cells on the same pair of bit segments share the two I/O SBDs (Schottky barrier diodes). In Fig. 2, the bit segments are N+ subdiffusions. During Access, the s...