Browse Prior Art Database

Parallel Microcode Access for Performance

IP.com Disclosure Number: IPCOM000061273D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Finney, D: AUTHOR

Abstract

This article describes a technique which reduces the number of cycles required for executing a floating-point function and branching on the result of that function. In previous microcoded machines, two or more machine cycles had to be executed to perform a function (e.g., add) and then branch to the next micro instruction based on the result of that function. This is because for performance reasons the next read-only storage (ROS) access is done in parallel and with the execution of the function such that the branch destination address could not be generated before the next ROS access must begin. The technique disclosed herein is illustrated in the block diagram of the drawing and requires only one cycle to execute a function and branch on the result without sacrificing the performance of accessing the ROS in parallel.

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Parallel Microcode Access for Performance

This article describes a technique which reduces the number of cycles required for executing a floating-point function and branching on the result of that function. In previous microcoded machines, two or more machine cycles had to be executed to perform a function (e.g., add) and then branch to the next micro instruction based on the result of that function. This is because for performance reasons the next read-only storage (ROS) access is done in parallel and with the execution of the function such that the branch destination address could not be generated before the next ROS access must begin. The technique disclosed herein is illustrated in the block diagram of the drawing and requires only one cycle to execute a function and branch on the result without sacrificing the performance of accessing the ROS in parallel. In order to accomplish this, there are two ROS arrays which are accessed in parallel using the same address. Each ROS entry contains a complete control word including the next ROS address, branch controls, and special address bit. The next ROS address is used to address both ROS arrays for the next access. The branch control bits select the conditions to be tested at the end of current cycle, and the special address bit is used to determine which ROS array is the base array. If the micro instruction does not require a branch, then the output of the branch logic will be a zero. This will result in the special bit directly selecting either ROS 0 or ROS 1. This allows all ROS locations to be direct...