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Low Power FET DTL NOR

IP.com Disclosure Number: IPCOM000061291D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Klimanis, V: AUTHOR [+3]

Abstract

This article describes a general-purpose logic circuit for gate arrays in which p-type FETs (field-effect transistors) are used as active pull-ups to perform a NOR function, with a resulting high performance and low power consumption. The DTL (diode-transistor logic) NOR function is similar to two, one-way DTL NAND circuits with dotted collectors, which produce a two-way NOR. A power saving is achieved with this circuit by the use of a complementary FET-bipolar NOR combined with a unique base drive resistor configuration.

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Low Power FET DTL NOR

This article describes a general-purpose logic circuit for gate arrays in which p- type FETs (field-effect transistors) are used as active pull-ups to perform a NOR function, with a resulting high performance and low power consumption. The DTL (diode-transistor logic) NOR function is similar to two, one-way DTL NAND circuits with dotted collectors, which produce a two-way NOR. A power saving is achieved with this circuit by the use of a complementary FET-bipolar NOR combined with a unique base drive resistor configuration. The characteristics of the circuit are: 1) The p-type FETs T1 and T2 are connected in series and have their gates connected to inputs 1 and 2 to provide a logical NAND pullup function and to replace the usual collector load resistor with elements that dissipate no quiescent power and that improve performance. 2) Base drive resistors R1 and R2 are connected from the input nodes to the base nodes of transistors T3 and T4 instead of the usual Vcc to T3 and T4 connections. This results in zero power dissipation in the base drive resistors when both inputs are down and improves turn-off speed by reducing the base drive as the input transition falls. Turn-on speed is improved, as compared with regular DTL, by the fast rise time produced by the p-FET pull-up devices in the previous stages. The performance of this circuit can be further improved by adding parallel capacitors C1 and C2 across the base drive resistors R1 and R2 to c...