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Multi-Chip on Tape Memory Packaging

IP.com Disclosure Number: IPCOM000061292D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Jokl, CH: AUTHOR [+2]

Abstract

A technique is described whereby memory circuit chips are mounted on a tape, utilizing conventional Tape Automated Bonding (TAB) technology. Leads from one frame, which contain a memory circuit chips, are interconnected to the next memory chip frame, as shown in Fig. 1, so as to provide a memory circuit of a predetermined "size". Wiring layout is dependent on chip pad assignment so that a two-layer tape will accommodate any memory configuration. The memory "strip" is then excised with the ends of the strips prepared for assembly to the next level carrier. The attachment to the carrier is processed by means of connector tape, thermocompression bonding or soldering. A form of encapsulation is then applied to protect the memory circuits. Memory chips 10, as shown in Fig.

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Multi-Chip on Tape Memory Packaging

A technique is described whereby memory circuit chips are mounted on a tape, utilizing conventional Tape Automated Bonding (TAB) technology. Leads from one frame, which contain a memory circuit chips, are interconnected to the next memory chip frame, as shown in Fig. 1, so as to provide a memory circuit of a predetermined "size". Wiring layout is dependent on chip pad assignment so that a two-layer tape will accommodate any memory configuration. The memory "strip" is then excised with the ends of the strips prepared for assembly to the next level carrier. The attachment to the carrier is processed by means of connector tape, thermocompression bonding or soldering. A form of encapsulation is then applied to protect the memory circuits. Memory chips 10, as shown in Fig. 2, are layered or stacked together, one on top of the other, using insulation material 11. Electrical connections 12, at the ends of the strips, are secured by means of tape, bonding or soldering. The primary advantage of this technique is flexibility in higher level packaging. The memory is mounted over other components 13, which in turn are mounted onto substrate 14. The memory circuit components can also be treated as flexible circuits. Furthermore, the technique offers advantages over prior-art fabrication methods, which use costly Dual Inline Packaging (DIP) technology.

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