Browse Prior Art Database

Interface Board for Feature Card Test

IP.com Disclosure Number: IPCOM000061306D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 91K

Publishing Venue

IBM

Related People

Bradicich, TM: AUTHOR [+3]

Abstract

This article describes a conversion for a personal computer (PC) family planar board which allows it to become a PC feature card test board. It provides a means for dynamic testing of several identical PC feature cards simultaneously residing on the PC bus. The design of the interface board for feature card test (IBFCT) is shown in the perspective view of Fig. 1. The IBFCT functions to convert an ordinary PC planar board into a test system where 8 identical feature cards may be individually tested with reliability, availability, serviceability (RAS) code, even though they all have the same address and reside on the common PC I/O bus. The IBFCT simply plugs into the J6 I/O slot of the PC planar and uses that CPU, thus eliminating the need for a new CPU design.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 2

Interface Board for Feature Card Test

This article describes a conversion for a personal computer (PC) family planar board which allows it to become a PC feature card test board. It provides a means for dynamic testing of several identical PC feature cards simultaneously residing on the PC bus. The design of the interface board for feature card test (IBFCT) is shown in the perspective view of Fig. 1. The IBFCT functions to convert an ordinary PC planar board into a test system where 8 identical feature cards may be individually tested with reliability, availability, serviceability (RAS) code, even though they all have the same address and reside on the common PC I/O bus. The IBFCT simply plugs into the J6 I/O slot of the PC planar and uses that CPU, thus eliminating the need for a new CPU design. The IBFCT also contains communication logic which is used to communicate with an external host PC. The host PC controls, sequences and accumulates data for the test process. Referring to the circuit diagram of Fig. 2, in order to isolate the PC feature cards that are not under test, the RESET (RST), AEN, AND A19 I/O lines are individually controlled for each of the 8 I/O slots. This is done by using D- type flip-flops, "OR" gates, and "Exclusive OR" gates. Each I/O line to be controlled has its own flip-flop and gate associated with it. Loading a flip-flop with a logic "1" will drive the corresponding RST and AEN lines high and cause the "Exclusive OR" gate to act as an...