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Direct Memory Access Controller With Intel 8237 Function and Extended Bus Interface

IP.com Disclosure Number: IPCOM000061317D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Zimmerman, JP: AUTHOR

Abstract

A method is described for modifying the design of an Intel 8237-type Direct Memory Access (DMA) controller chip to allow almost full bus control during DMA transfers without the need for peripheral bus-handling logic. In the normal IBM Personal Computer environment, an Intel 8237 DMA controller and many auxiliary logic chips are used to generate complete bus cycles during DMA transfers. The 8237 generates addresses during DMA cycles to access memory, but only uses 8 lines to generate the addresses. It generates a 16-bit address by strobing the upper 8 bits onto an external address latch. The 8237 makes no provision for the upper 4 address bits needed for a full 20-bit address. Also, no address latch is provided since the 8237 assumes it is interfacing with a fully de-multiplexed address/data bus.

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Direct Memory Access Controller With Intel 8237 Function and Extended Bus Interface

A method is described for modifying the design of an Intel 8237-type Direct Memory Access (DMA) controller chip to allow almost full bus control during DMA transfers without the need for peripheral bus-handling logic. In the normal IBM Personal Computer environment, an Intel 8237 DMA controller and many auxiliary logic chips are used to generate complete bus cycles during DMA transfers. The 8237 generates addresses during DMA cycles to access memory, but only uses 8 lines to generate the addresses. It generates a 16-bit address by strobing the upper 8 bits onto an external address latch. The 8237 makes no provision for the upper 4 address bits needed for a full 20-bit address. Also, no address latch is provided since the 8237 assumes it is interfacing with a fully de- multiplexed address/data bus. This requires external logic to maintain a de- multiplexed bus, logic to maintain a 16-bit address, and logic to maintain the 4 high-order addresses that are independent of the DMA controller. For an environment that attempts to minimize external logic and uses a fully multiplexed 20-bit address/data bus, the following design (based on the 8237 function) was implemented: * full 20-bit addresses are placed on the bus during the address generation portion of every DMA transfer - no external latches required * lower 8 address bits become tri-stated during the data transfer portion of every DMA transfer to allow data to be placed on the bus, thus preserving a fully multiplexed bus * an address latch strobe is generated during the address generation portion of every DMA tr...