Browse Prior Art Database

Automatic Synthesis of I/0 Wire Areas

IP.com Disclosure Number: IPCOM000061318D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Lleonart, G: AUTHOR

Abstract

A technique is described whereby input/output (I/O) port wiring of very large-scale integrated (VLSI) circuit chips is maximized through the use of an automatic synthesis computer program. With the advent of large multiple plane VLSI chips, storage requirements to process chip wiring have increased tremendously. As a result, it is extremely difficult, if not impossible, to wire a large VLSI chip in one operation using a typical "maze runner" program. As a result, methods have been developed that segment the chip so as to allow a wiring program to process the segments separately, then joining the segments together at the end of the program. The technique described herein provides a method of processing I/O areas in a modular manner.

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Automatic Synthesis of I/0 Wire Areas

A technique is described whereby input/output (I/O) port wiring of very large- scale integrated (VLSI) circuit chips is maximized through the use of an automatic synthesis computer program. With the advent of large multiple plane VLSI chips, storage requirements to process chip wiring have increased tremendously. As a result, it is extremely difficult, if not impossible, to wire a large VLSI chip in one operation using a typical "maze runner" program. As a result, methods have been developed that segment the chip so as to allow a wiring program to process the segments separately, then joining the segments together at the end of the program. The technique described herein provides a method of processing I/O areas in a modular manner. Typically "maze runners" require large storage so as to read the entire wiring map of the chip into virtual storage. Only a small portion of the chip is used to wire I/O ports to the books within the logic area. The programming system described herein automatically segments the chip I/O by creating four rectangular non-overlapping areas so as to connect the I/O ports to the chip logic. Therefore, by using this technique, the storage required to process any of the I/O areas is a very small portion of the storage needed to wire the entire chip. The inputs are handled through the use of three tables and two files. Table 1 contains the placement of driver and receivers which might be generated manually or by a placement program. Table 2 indicates the displacement of drivers and receivers in wiring channels from the logic area origin. Table 3 indicates the displacement of the driver/receiver pins with respect to the starting position of the driver/receiver cell. File 1 contains the starting position and size of the four I/O wire areas. File 2 contains the names of the logic groups or macros which connect to the I/O ports. The edges of the logic groups that contain the logic service terminals (LSTs) which connect to the I/O ports are also identified. The processing of the program requires eight...