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Browse Prior Art Database

Bus Design in a High Capacitance Environment

IP.com Disclosure Number: IPCOM000061330D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Hanna, JT: AUTHOR [+2]

Abstract

A bus design is described which allows CMOS drivers to drive high speed signals in a high capacitance environment. Normally, a trade-off exists between speed and capacitive loading when CMOS technology is used to drive logic signals. In the bus environment shown in Fig. 1, the unmultiplexed address/ data lines AD(O-7) tend to be very popular signals. They are used by memory, the microprocessor, I/O devices contained within the unit, and by any externally attached devices. Capacitance is relatively large on these lines since each component using these signals adds a capacitive load, and the additional board wiring also adds capacitance. The switching speed of a CMOS gate is a function of the capacitive load on the gate's output.

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Bus Design in a High Capacitance Environment

A bus design is described which allows CMOS drivers to drive high speed signals in a high capacitance environment. Normally, a trade-off exists between speed and capacitive loading when CMOS technology is used to drive logic signals. In the bus environment shown in Fig. 1, the unmultiplexed address/ data lines AD(O-7) tend to be very popular signals. They are used by memory, the microprocessor, I/O devices contained within the unit, and by any externally attached devices. Capacitance is relatively large on these lines since each component using these signals adds a capacitive load, and the additional board wiring also adds capacitance. The switching speed of a CMOS gate is a function of the capacitive load on the gate's output. Due to the large capacitive load on the address/data lines AD(O-7), the output buffers used by the CMOS gate arrays would be unable to place data onto the bus in the required amount of time. To eliminate this problem, the address/data bus was split into two buses, with a CMOS buffer re-driving the bus. The buffer is able to drive a larger capacitive load, and it also splits the total capacitance load between the processor/RAM/ROM and the I/O channel. Gate array #2 contains the logic to drive the direction and enable signals to the channel address/data (CHAD) buffer. Normally, the CHAD buffer is enabled in driving data from the processor side to the I/O side. The following situations cause gate array #2 to drive data from the I/O side to the processor side: * any I/O read * a memory read from the display RAM (random-access memory) * a memory read from any memory other than...