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Hardware-Assisted Byte Alignment for High-Speed Digital Communications Processors

IP.com Disclosure Number: IPCOM000061331D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Siegel, SJ: AUTHOR

Abstract

A technique is described whereby byte alignment in a communications processor allows the processor to move data stored at even/odd locations to odd/even locations between system and local storage without any inefficient double transfers or direct memory address (DMA) reprogramming. Aligned transfers are also supported. In prior art, a high speed input/output attachment (IOA) is required to buffer data received from its interface, such as a local area network (LAN) prior to moving the data to local storage. By using the technique described herein, that of hardware-assisted byte alignment, data may be moved directly from the buffered IOA into a specified address space alignment, thereby eliminating an intermediate transfer to local storage.

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Hardware-Assisted Byte Alignment for High-Speed Digital Communications Processors

A technique is described whereby byte alignment in a communications processor allows the processor to move data stored at even/odd locations to odd/even locations between system and local storage without any inefficient double transfers or direct memory address (DMA) reprogramming. Aligned transfers are also supported. In prior art, a high speed input/output attachment (IOA) is required to buffer data received from its interface, such as a local area network (LAN) prior to moving the data to local storage. By using the technique described herein, that of hardware-assisted byte alignment, data may be moved directly from the buffered IOA into a specified address space alignment, thereby eliminating an intermediate transfer to local storage. This approach reduces the bandwidth load on the processor, thereby increasing the overall processing performance. Byte alignment 10, as shown in Fig. 1, is positioned between base- Z 11 and DMA control 12, so as to eliminate the controller's inability to change from byte/word/byte mode in the space of one DMA transfer. By intercepting data strobes to base-Z, byte alignment 10 enables DMA control 12 to always be programmed in word mode. Byte alignment 10 uses commands within base-Z's address space. Start DMA commands to base-Z 11 are used to initialize the byte alignment hardware. Two base-Z 11 commands are used to read status and the contents of sa...