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Method to Generate an Automatic Wait-State During Direct Memory Access

IP.com Disclosure Number: IPCOM000061334D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Hanna, JT: AUTHOR [+2]

Abstract

A method is described to automatically include a wait state during direct memory access (DMA) transfers to satisfy the standard I/O device access timings without the need for external wait signal generation. In a bus environment for a Personal Computer (PC) where all I/O read and write cycles are 5 clock cycles long (as opposed to 4 clock cycles for memory accesses), DMA cycles which perform an I/O cycle concurrent with a memory cycle must also be 5 clock cycles long. The IBM PC and PC XT use the 8237 DMA controller chip to perform DMA transfers. The 8237 normally only allows 3 clock cycles for a DMA transfer, with an input signal (+READY) used to extend this transfer cycle.

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Method to Generate an Automatic Wait-State During Direct Memory Access

A method is described to automatically include a wait state during direct memory access (DMA) transfers to satisfy the standard I/O device access timings without the need for external wait signal generation. In a bus environment for a Personal Computer (PC) where all I/O read and write cycles are 5 clock cycles long (as opposed to 4 clock cycles for memory accesses), DMA cycles which perform an I/O cycle concurrent with a memory cycle must also be 5 clock cycles long. The IBM PC and PC XT use the 8237 DMA controller chip to perform DMA transfers. The 8237 normally only allows 3 clock cycles for a DMA transfer, with an input signal (+READY) used to extend this transfer cycle. The IBM PC contains external logic gates to determine when a DMA transfer is taking place, and manipulates the +READY line to insert two additional wait states. The I/O device involved in the DMA transfer may also manipulate the +READY line to insert even more wait states. This is used by slower I/O devices. The following were incorporated into the DMA controller via the state machine that controls the flow of execution. * Two wait cycles are automatically incorporated into all DMA transfer cycles * External devices can extend the cycle time of DMA transfers by manipulating an input signal to the DMA controller (+IOCHNRDY) Four J K flip-flops control the 8 states that comprise the state machine which times and controls the DMA. The state machine keeps track of the bus, memory timing, and the I/O devices using the DMA's channels. The various states are explained below. SI-Idle State In state SI the DMA controller is waiting for a transfer request. If a DMA request occurs and is not masked by the mask register or the command register, or a software DMA request is issued, the DMA requests the Central Processing Unit (CPU) to release the bus (by momentarily lowering the -RQ/GT1 line) and moves to state SO. Programming the DMA occurs concurrently with state SI. There is no possibility of DMA transfers occurring while the DMA controller is being programmed since the processor only acknowledges the -RQ/GT1 signal after a completed instruction cycle. SO-DMA Transfer Wait Cycle During state SO the DMA is waiting for a confirmation of the bus release from the CPU. Following the confirmation (-RQ/GT1 going low), the state machine proceeds to state S1. S1-Bus Released by CPU State S1 occurs when the CPU has acknowledged the DMA's bus release request. Bus signal AEN becomes active during this state. The state machine unconditionally proceeds to state S2. S2-Addresses Placed on the Bus State S2 is the first step of the actual data transfer. During this state, memory addresses are placed on the bus and the address latch enable line (+ALE) signals valid address information on address lines A19-A8 and AD7-AD0. During this state the DMA controller takes charge of the -IOR and -MEMR bidirectional lines. This...