Browse Prior Art Database

Partitioning of Video Memory for Improved CPU Access

IP.com Disclosure Number: IPCOM000061335D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Shore, AB: AUTHOR

Abstract

A technique is described whereby a video memory, as used in buffer circuitry of cathode ray tube (CRT) graphic adapter circuitry, is partitioned so as to provide greater access to a computer's central processing unit (CPU). In prior art, CPU accesses to video memory were interspersed among the CRT refresh memory accesses at a ratio of one CPU access to five or more CRT accesses, resulting in delays in buffer updating. The technique described herein provides a significant increase in CPU access through the use of memory partitions. Control logic, as shown in the block diagram, is provided first to determine if the CPU address in partition is being scanned. If it is, then the CPU cycle is held for a regular interspersed cycle. If it is not, determination is made to see if the next partition is to be scanned.

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Partitioning of Video Memory for Improved CPU Access

A technique is described whereby a video memory, as used in buffer circuitry of cathode ray tube (CRT) graphic adapter circuitry, is partitioned so as to provide greater access to a computer's central processing unit (CPU). In prior art, CPU accesses to video memory were interspersed among the CRT refresh memory accesses at a ratio of one CPU access to five or more CRT accesses, resulting in delays in buffer updating. The technique described herein provides a significant increase in CPU access through the use of memory partitions. Control logic, as shown in the block diagram, is provided first to determine if the CPU address in partition is being scanned. If it is, then the CPU cycle is held for a regular interspersed cycle. If it is not, determination is made to see if the next partition is to be scanned. If the next partition is not to be scanned, then the CPU is allowed to access memory. If the next partition is to be scanned, then a CPU cycle is held so that a regular interspersed cycle may occur. The improvement in CPU access time of as much as seventy-five percent is due to the fact that if four partitions are used, three of the partitions are unused at any one time by the CRT refresh scan. Increasing the number of partitions will increase the access availability of the CPU.

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