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Signal Encoding for Fiber-Optic Link

IP.com Disclosure Number: IPCOM000061339D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Rice, AJ: AUTHOR

Abstract

Communication Controllers are made to enable digital processors to communicate over high-speed communication links using fiber-optic cables. Assuming an HDLC data stream is being generated, then means should be provided to enable recovering, at the receiving end, a clock signal (RC) correctly synchronized with the data (RD). A solution is provided here which applies NRZI coding to an HDLC data stream. A clockless, NRZI, transmission coding is used which offers twice the data, for a given bandwidth, compared to usually used coding for fiber-optic data links. The HDLC protocol defines the start and end of an information frame by a "flag" consisting of six consecutive "1" bits. If, in the frame, there is a succession of "1" bits to be transmitted, a "0" bit is inserted after five consecutive "1" bits.

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Signal Encoding for Fiber-Optic Link

Communication Controllers are made to enable digital processors to communicate over high-speed communication links using fiber-optic cables. Assuming an HDLC data stream is being generated, then means should be provided to enable recovering, at the receiving end, a clock signal (RC) correctly synchronized with the data (RD). A solution is provided here which applies NRZI coding to an HDLC data stream. A clockless, NRZI, transmission coding is used which offers twice the data, for a given bandwidth, compared to usually used coding for fiber-optic data links. The HDLC protocol defines the start and end of an information frame by a "flag" consisting of six consecutive "1" bits. If, in the frame, there is a succession of "1" bits to be transmitted, a "0" bit is inserted after five consecutive "1" bits. The inserted "0" bits are removed at the receiving end. However, the number of successive "0" bits, in a frame, is unlimited. Hence, to guarantee a transition rate enabling clock recovery, the HDLC bit stream should be coded in NRZI (non-return to zero inverted). This means that the previous binary level (high or low) is maintained for a "1" bit, while the previous level is inverted for "0" bit. At the receiver, a clock recovery circuit is used to recover the clock signal (RC) from the received signal. The clock recovery circuit is made to maintain the correct frequency and phase relationship between RC and RD by synchronizing RC ea...