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CLOCK Recovery Circuit Based on Preset Counter

IP.com Disclosure Number: IPCOM000061343D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Rice, AJ: AUTHOR

Abstract

In a 2 Mbps clockless network the receive clock signal must be derived from the received data stream. This is a clock recovery circuit which has two functional parts, i.e., an elastic clock and a synchronizer. The elastic clock can produce a nominal cycle of 500 ns, a stretched cycle of 560 ns and a shrunk cycle of 440 ns. Each time there is a positive-going transition on received data signal RD, the synchronizer compares the clock cycle to this transition and defines the length of the next clock cycle to cause synchronization with the data. The clock includes a presettable counter 10. This counter counts up in sequence (at a given CK cadence of, for instance, 16 MHz) until a "load" signal is active. The timing decoder 12 is made to generate the load signal when a count of B (hexadecimal) is reached.

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CLOCK Recovery Circuit Based on Preset Counter

In a 2 Mbps clockless network the receive clock signal must be derived from the received data stream. This is a clock recovery circuit which has two functional parts, i.e., an elastic clock and a synchronizer. The elastic clock can produce a nominal cycle of 500 ns, a stretched cycle of 560 ns and a shrunk cycle of 440 ns. Each time there is a positive-going transition on received data signal RD, the synchronizer compares the clock cycle to this transition and defines the length of the next clock cycle to cause synchronization with the data. The clock includes a presettable counter 10. This counter counts up in sequence (at a given CK cadence of, for instance, 16 MHz) until a "load" signal is active. The timing decoder 12 is made to generate the load signal when a count of B (hexadecimal) is reached. Under normal operating conditions at the load signal, the counter is preset by circuit 14 to a given value (e.g., 4) to generate the nominal cycle. Should the clock cycle be stretched or shrunk, then the counter would start counting at a different presettable value (e.g., 3 or 5). The RC signal is directly generated using the counter QD stage output. A clock window (CW) signal generated by circuit 12 is centered on the rising edge of the nominal clock signal and lasts for two oscillator periods. When the clock is correctly synchronized with data, any data transition should occur within the clock window time. This conditi...