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Confirmed Prefetching With Confirmation on Exit

IP.com Disclosure Number: IPCOM000061345D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

When prefetching next sequential instruction lines into a shared or split cache, it is worthwhile to perform confirmed prefetching, that is, to prefetch only if prefetching was successful the last time it was attempted. An extension of this idea is to confirm prefetching if there is a good reason to believe that the action is correct. In the present approach, an array is maintained by line identifier which has a bit per line. The bit signals on an MRU (Most Recently Used) change to line X, say, that the next sequential line X + l should be prefetched. If X + l is not in the cache, it is prefetched, and in an ordinary scheme if X + l is used, the prefetch is confirmed. As an alternative, the present approach confirms the prefetch on exit rather than on entry.

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Confirmed Prefetching With Confirmation on Exit

When prefetching next sequential instruction lines into a shared or split cache, it is worthwhile to perform confirmed prefetching, that is, to prefetch only if prefetching was successful the last time it was attempted. An extension of this idea is to confirm prefetching if there is a good reason to believe that the action is correct. In the present approach, an array is maintained by line identifier which has a bit per line. The bit signals on an MRU (Most Recently Used) change to line X, say, that the next sequential line X + l should be prefetched. If X + l is not in the cache, it is prefetched, and in an ordinary scheme if X + l is used, the prefetch is confirmed. As an alternative, the present approach confirms the prefetch on exit rather than on entry. Specifically, the confirmation on exit is done as follows: - When a prefetch is initiated on the basis of a confirmation bit, the bit is turned off. - On exit of line L from the cache, the cache directory is interrogated for the concurrent residence of line L-1 and line L+1. If L-1 is in the cache, the confirmation bit for L-1 is turned on. If L+1 is in the cache, the confirmation bit for line L is turned on. Care must be taken that the line prefetched is actually accessed while in the cache. This can be accomplished by the use of a prefetch buffer assuming that only accessed lines are placed in the cache. Another approach is to flag prefetched but unaccessed li...