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Fault Identification in Shift Registers for Reliability Evaluation

IP.com Disclosure Number: IPCOM000061350D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Lalande, R: AUTHOR [+3]

Abstract

The device shown above allows the faults in shift registers to be located for failure-analysis purposes. It requires a few additional pieces of hardware and makes fault identification easy by testing. Shift registers are widely used in logic design and in part numbers used for characterization and reliability purposes. Conventional techniques allow one to determine if the shift register operates or not. They do not permit accurate identification of faults. In the Fig. 1, eight shift registers, labelled A to H, of eight bits each are shown. A logic arrangement of NAND gates provides a stuck at 0 detection at S0, and a logic arrangement of NOR gates provides a stuck at 1 detection at S1. A common input test pattern is provided to the 8 data inputs. Outputs A to H are supposed to be observable.

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Fault Identification in Shift Registers for Reliability Evaluation

The device shown above allows the faults in shift registers to be located for failure-analysis purposes. It requires a few additional pieces of hardware and makes fault identification easy by testing. Shift registers are widely used in logic design and in part numbers used for characterization and reliability purposes. Conventional techniques allow one to determine if the shift register operates or not. They do not permit accurate identification of faults. In the Fig. 1, eight shift registers, labelled A to H, of eight bits each are shown. A logic arrangement of NAND gates provides a stuck at 0 detection at S0, and a logic arrangement of NOR gates provides a stuck at 1 detection at S1. A common input test pattern is provided to the 8 data inputs. Outputs A to H are supposed to be observable. The test patterns for the stuck at 0 and stuck at 1 detection are shown in Fig. 1. The delays are given in clock periods, T0 being the period of the register clock of the eight shift registers. The first eight periods are used for initialization of all shift register stage outputs at 0 or 1. At a time equal to 9T0, a pulse at UP or DOWN level is propagated through the shift registers. For the stuck at 0 detection, during the initialization, output S0 is at a down level, even if there is a fault. Between time 8T0 and 16T0, S0 should remain at 1 if no fault has occurred. If there is a fault, the time at which S0...