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Memory Expansion for Microprocessor

IP.com Disclosure Number: IPCOM000061352D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Barucchi, G: AUTHOR

Abstract

Most microprocessors have an addressing capability of 64K half words in a directly addressable control storage which corresponds to a 16-bit address bus provided by the microprocessor. In some applications there is a need to have an expansion of the control store. This article relates to a solution for increasing the memory size. It is based on the fact that in general the microcode stored in the memory may be split into two parts: the microcode instructions and the data. The data are stored in one control store CSM2, and the microcode instructions in another control store CSM1, both being addressed by the same address bus from the microprocessor. Moreover, the CSM1 is also addressed from the machine incorporating the memory to fetch or store data by cycle steal.

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Memory Expansion for Microprocessor

Most microprocessors have an addressing capability of 64K half words in a directly addressable control storage which corresponds to a 16-bit address bus provided by the microprocessor. In some applications there is a need to have an expansion of the control store. This article relates to a solution for increasing the memory size. It is based on the fact that in general the microcode stored in the memory may be split into two parts: the microcode instructions and the data. The data are stored in one control store CSM2, and the microcode instructions in another control store CSM1, both being addressed by the same address bus from the microprocessor. Moreover, the CSM1 is also addressed from the machine incorporating the memory to fetch or store data by cycle steal. When an instruction located in memory CSM2 is used to fetch or store data from CSM1, this operation requires 2 cycles: - During the first cycle the instruction is read from memory CSM2 and set in the microprocessor. In this case CSM2 is addressed. - During the second cycle the data is fetched from or stored in memory CSM1. In this case CSM1 is addressed. A control wire, called "Extended Operation Out", from the microprocessor becomes active during the first cycle of a two-cycle instruction. The two-cycle instructions of the microprocessor instruction set are: -Control store store instruction (CS0 or CS1) - Control store fetch instruction (CS0 or CS1) - Register to register instruction ex...