Browse Prior Art Database

Mask Control of Additional Address Space Keys for Series/1 Processor

IP.com Disclosure Number: IPCOM000061428D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Bourke, D: AUTHOR [+7]

Abstract

A mask is used to control the selection and use of an additional source of address space keys in the IBM Series/1 data processor. Additional machine instructions are provided for setting, changing and reading the mask bits. The larger models of the IBM Series/1 processors employ an address translator for converting a 16-bit logical address into a 24-bit physical address for addressing the main storage unit associated with the processor. This address translation mechanism is described in U.S. Patent 4,037,215. The pertinent portions of this address translator are shown in a simplified manner in Fig. 1. In a typical case, the 16-bit logical address is obtained from one of the 16-bit general purpose registers in the processor local storage unit 9.

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Mask Control of Additional Address Space Keys for Series/1 Processor

A mask is used to control the selection and use of an additional source of address space keys in the IBM Series/1 data processor. Additional machine instructions are provided for setting, changing and reading the mask bits. The larger models of the IBM Series/1 processors employ an address translator for converting a 16-bit logical address into a 24-bit physical address for addressing the main storage unit associated with the processor. This address translation mechanism is described in U.S. Patent 4,037,215. The pertinent portions of this address translator are shown in a simplified manner in Fig. 1. In a typical case, the 16-bit logical address is obtained from one of the 16-bit general purpose registers in the processor local storage unit 9. One such register is represented by the segment and byte displacement fields of the extended general purpose register 10. The byte displacement bits are supplied directly to the lower-order bit positions of the storage address in a group of segmentation register stacks
12. A particular one of the segmentation register stacks is selected by means of one of the address space keys OP1K, OP2K and ISK obtained from an address key register (AKR) 13. The particular key to be used is selected by key select circuit 14 which is controlled by appropriate signals from the processor. Heretofore, the output key from key select circuit 14 has been supplied directly to the stack-selecting mechanism of the segmentation register stacks 12. Thus, the selected key from AKR 13 would select a particular stack, and the segment bits from the general purpose register 10 would select a particular register in the selected stack. The 13 address bits in the selected segmentation register are then supplied to the higher-order bit positions in the storage address register 11. The various segmentation registers are loaded with the desired address values during the initial program load operations which are performed before the programs are run. Currently,...