Browse Prior Art Database

Use of Parameter Field in Index Stack Register to Insure System Integrity

IP.com Disclosure Number: IPCOM000061429D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Bourke, D: AUTHOR [+8]

Abstract

In a double-indexed key system for extended addressing with multiple Address Space Index Stack (ASIS) images in storage, protection against invalid images is necessary. A method is described here to insure system integrity through limit checking on ASIS length via a parameter stored in the index stack register. Reference is made to the preceding article that is of interest.

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Use of Parameter Field in Index Stack Register to Insure System Integrity

In a double-indexed key system for extended addressing with multiple Address Space Index Stack (ASIS) images in storage, protection against invalid images is necessary. A method is described here to insure system integrity through limit checking on ASIS length via a parameter stored in the index stack register. Reference is made to the preceding article that is of interest. The following expressions are sometimes used herein: ASIR Address Space Index Register ASIS Address Space Index Stack EAKR Extended Address Key Register EGPR Extended General Purpose Register ELSR Extended Level Storage Register GPR General Purpose Register GRAM General Register Active Mask GRI General Register Index ISI Instruction Space Index LSR Level Status Register OP1I Operand One Index (Controls Access of Data from Storage) OP2I Operand Two Index (Controls Access of Data into Storage) An Extended Addressing feature is described herein that may be used with the IBM Series/1 processor, for example. This feature (EAS/1) provides the capability for application programs to address more than 64 KB of logical storage. Also, the EAS/1 architecture allows operating systems to efficiently support more than 512 KB of physical storage. The general approach is to provide a minimum of 24 bits of addressing (linear space) in a manner that does not require complete redefinition of the architecture or instruction set. Furthermore, to minimize software redesign, the resultant architecture preserves the software design dependencies on the Series/1 architecture. Within these constraints, the 16 MB of linear addressing is achieved by extending the existing base/ displacement addressing mode of the Series/1. In the current Series/1, the GPR can contain either the base or the displacement value. With the EAS/1 architecture, the extended register always forms a base which can point anywhere within a 16 MB range. In order to extend the effective base without recoding or reformatting the instructions, the concept of indirect address keys is utilized. Reference is made to the drawing. Associated with each of the 8 GPRs is a 16-bit ASIR. Together, the GPR-ASIR register pair is referred to as an Extended GPR (EGPR), designated 1. The ASIR is used whenever the associated GPR is utilized in an effective address calculation. Each ASIR contains an 8-bit GRI which is used to locate the actual Series/1 address key. The actual Series/1 address keys (logical keys) reside in a 256 x 2 byte stack 2 referred to as the ASIS. The ASIS is built by the operating system and resides in the supervisor's space in physical main storage. Thus, the GRI acts as an index into the ASIS entry which contains the logical key necessary for the formation of the logical effective address. A GRAM, ASIS Validity Bit* and EAKR may be added to the Series/1 architecture. Since the ASIS is in the supervisor space in main storage, an Index Stack R...