Browse Prior Art Database

Method of Controlling Dual Mode Operation of a Series/1 Processor With Extended Addressing (Address Space Indexing)

IP.com Disclosure Number: IPCOM000061435D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Bourke, D: AUTHOR [+8]

Abstract

Existing programs written on a conventional IBM Series/1 processor are allowed to run on a Series/1 processor having extended addressing capability by providing for a dual mode operation. Reference is made to the articles on pages 968 and 974 of this issue that are of interest. The following expressions are sometimes used in the various articles including the present article. Reference is made to the drawings of the aforementioned articles for the elements listed.

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Method of Controlling Dual Mode Operation of a Series/1 Processor With Extended Addressing (Address Space Indexing)

Existing programs written on a conventional IBM Series/1 processor are allowed to run on a Series/1 processor having extended addressing capability by providing for a dual mode operation. Reference is made to the articles on pages 968 and 974 of this issue that are of interest. The following expressions are sometimes used in the various articles including the present article. Reference is made to the drawings of the aforementioned articles for the elements listed. ASIR Address Space Index Register ASIS Address Space Index Stack EAKR Extended Address Key Register EGPR Extended General Purpose Register ELSR Extended Level Status Register GPR General Purpose Register GRAM General Register Active Mask GRI General Register Index ISI Instruction Space Index LSR Level Status Register OP1I Operand One Index (Controls Access of Data from Storage) OP2I Operand Two Index (Controls Access of Data into Storage) In these articles, an Extended Addressing feature is described that may be used with the IBM Series/1 processor, as an example.

This feature (EAS/1) provides the capability for application programs to address more than 64 KB of logical storage. Also, the EAS/1 architecture allows operating systems to efficiently support more than 512 KB of physical storage.

The general approach is to provide a minimum of 24 bits of addressing (16 MB linear space) in a manner that does not require complete redefinition of the architecture or instruction set. Furthermore, to minimize software redesign, the resultant architecture preserves the software design dependencies on the Series/1 architecture. Within these constraints, the...