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Saving the Current ADDRESS When Linking Across ADDRESS Spaces in a Processor Having Extended Addressing

IP.com Disclosure Number: IPCOM000061436D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Bouke, D: AUTHOR [+7]

Abstract

When linking across address spaces in a processor, it is necessary to save not only the Instruction Address Register (IAR) of the "from" instruction, but also the address space it was in. Modifications to the link instructions are described which may be used to save the "from" instruction key in the Address Space Index Register (ASIR) associated with the "return" register. For supplementary background information, reference is made to the article on page 974 of this issue.

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Saving the Current ADDRESS When Linking Across ADDRESS Spaces in a Processor Having Extended Addressing

When linking across address spaces in a processor, it is necessary to save not only the Instruction Address Register (IAR) of the "from" instruction, but also the address space it was in. Modifications to the link instructions are described which may be used to save the "from" instruction key in the Address Space Index Register (ASIR) associated with the "return" register. For supplementary background information, reference is made to the article on page 974 of this issue. The following expressions are sometimes used in connection with the Extended Addressing system in addition to other terms: ASIR Address Space Index Register ASIS Address Space Index Stack EAKR Extended Address Key Register EGPR Extended General Purpose Register ELSR Extended Level Status Register GPR General Purpose Register GRAM General Register Active Mask GRI General Register Index ISI Instruction Space Index LSR Level Status Register OP1I Operand One Index (Controls Access of Data from Storage) OP2I Operand Two Index (Controls Access of Data into Storage) Jump and Link Reference is made to the Jump and Link layout (Fig. 1). The updated contents of the Instruction Address Register (the location of the next sequential instruction) are stored into the register specified by the R field. If extended addressing is enabled, the current ISI is copied from the Extended AKR to bits 8-15 of the ASIR specified by the R field. Bits 0-7 of the ASIR are set to zero. Bit 8 of the Word Displacement field is propagated left by seven bit positions and a zero is appended at the low-order end, resulting in a 16-bit word. This value is added to the contents of the updated Instruction Address Register, and the result stored in the Instruction Address Register, becoming the address of the next instruction to be fetched. All indicators are unchanged. Exceptions: Addressing - The effective address is outside the fitted storage size of the system. A program check interruption occurs with Invalid Storage Address set in the PSW (Program Status Word). Branching will not occur, but the storing of the updated instruction address into the register specified by the R field will still occur. Branch and Link Short Refer to the Branch and Link Short layout (Fig. 2). The updated contents of the Instruction Address Register (the location of the next sequential instruction) are stored in Register seven. If extended addressing is enabled, the current ISI is copied from the Extended AKR to ASIR 7 bits 8-15. ASIR 7 bits 0-7 are set to 0.

Bit 8 of the Word Displacement field is propagated left by seven bit positions and a zero is appended at the low-order end, resulting in a 16-bit word. This value is added to the contents of the register specified by R to form an Effective Address. The contents of the storage location specified by the Effective Address are stored in the Instruction to be fetched. A...