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Use of a Second Set of General Purpose Registers to Allow Changing General Purpose Registers During Conditional Branch Resolution

IP.com Disclosure Number: IPCOM000061437D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+4]

Abstract

A second set of general purpose registers (GPRs) and a tagging scheme are used which allow changes to GPRs along predicted paths in conditional executions. At most, one such predicted change is possible for each GPR. In high performance processors "guessing" at the direction that an instruction stream will proceed on a conditional branch because the conditions to resolve branch direction are not available is a technique that is well known and utilized. (A history of past branch decisions is usually used to educate the "guess".) None of the IBM System/360 or 370 processors has allowed an architected register or storage to be modified by these "conditional" instructions. Thus, the instructions in the "guessed" instruction stream direction can proceed only as long as this restriction causes no logical or physical "gate".

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Use of a Second Set of General Purpose Registers to Allow Changing General Purpose Registers During Conditional Branch Resolution

A second set of general purpose registers (GPRs) and a tagging scheme are used which allow changes to GPRs along predicted paths in conditional executions. At most, one such predicted change is possible for each GPR. In high performance processors "guessing" at the direction that an instruction stream will proceed on a conditional branch because the conditions to resolve branch direction are not available is a technique that is well known and utilized. (A history of past branch decisions is usually used to educate the "guess".) None of the IBM System/360 or 370 processors has allowed an architected register or storage to be modified by these "conditional" instructions. Thus, the instructions in the "guessed" instruction stream direction can proceed only as long as this restriction causes no logical or physical "gate". The described scheme is aimed at allowing the sink GPRs of the conditional stream to be modified, and then, if necessary, to allow their recovery to the original contents if the "guess" is incorrect. In order to maintain simplicity and speed in application, only one conditional recovery of each GPR is allowed. For each GPR (GPR1) there will be a second GPR (GPR2) that will be used to store the contents of GPR1 whenever a "conditional" instruction will modify GPR1. The figure shows a potential implementation. GPR1 has in addition to the gates shown in the figure all the ingates, outgates and other supporting hardware that the CPU design requires. The operation of the facilities shown in the figure is as follows: 1. When a conditional instruction is to modify a GPR during its execution, and if the GPR has not been modified by a previous conditional instruction in the same conditional stream - (a conditional instruction in conditional instruction stream N+l cannot modify a GPR modified by a conditional instruction in conditional instruction stream N until the N stream is resolved to be correctly guessed) - then, prior to the instruction execution, GPR1 is gated to GPR2 and the conditional mode tag (CMT)* is gated to the conditional mode tag field (CMTF) of the GPR2. *High performance processors may want to pass through several conditional branch instructions before any conditional strings of instructions are resolved. It is proposed tha...