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Browse Prior Art Database

Multi-Function Latches

IP.com Disclosure Number: IPCOM000061440D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Mitchell, RC: AUTHOR [+2]

Abstract

A simple single-input polarity-hold (PH) latch, which is shown in Fig. 1, has the potential for being reused as part of more complex latch functions. This allows a simple latch design to service the logical needs of an entire chip or an entire circuit family. The following describes a SET-RESET (SR) and a J-K Latch designed in this manner. Fig. 2 gives the schematic of the SET-RESET Latch. The simple polarity-hold latch is shown with its two inputs: Data and Clock. The RESET line drives the Data port of the PH latch, and the output of the four-device input circuit drives the clock port. The four-device input circuit will enable the PH latch clock input as long as RESET and SET are not both equal to '1'. If either R or S is not equal to '1', the state of the latch can change as a function of R on the data port.

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Multi-Function Latches

A simple single-input polarity-hold (PH) latch, which is shown in Fig. 1, has the potential for being reused as part of more complex latch functions. This allows a simple latch design to service the logical needs of an entire chip or an entire circuit family. The following describes a SET-RESET (SR) and a J-K Latch designed in this manner. Fig. 2 gives the schematic of the SET-RESET Latch. The simple polarity-hold latch is shown with its two inputs: Data and Clock. The RESET line drives the Data port of the PH latch, and the output of the four-device input circuit drives the clock port. The four-device input circuit will enable the PH latch clock input as long as RESET and SET are not both equal to '1'. If either R or S is not equal to '1', the state of the latch can change as a function of R on the data port. RESET itself determines the data input since this SET-RESET Latch is RESET dominant. If RESET is '0', the latch will reset. If RESET is '1', the latch will set if SET is '0' to allow the output of the four-device input circuit to be '1'. If RESET is '1', the latch will not change if SET = 1, since the PH clock input will be '0'. The C1 Clock input to the four-device circuit is the master clock for the SET- RESET latch. The PH clock input can be to 1 only when C1 CLOCK = 0. Therefore, all SET-RESET Latch changes will occur when C1 CLOCK goes low. The features of this SR Latch are the four-device input circuit to develop the PH clock, the use of RESET for the PH data, and the use of a simple polarity-hold latch. These features result in fewer devices and less silicon area than in the traditional, cross-coupled, two-sided SET-RESET latch. Also, a single, simple PH latch design can be used to support both the PH function and the SET-...