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CMOS Process for Titanium Salicide Bridging of a Trench and Simultaneously Allowing for True Gate Isolation

IP.com Disclosure Number: IPCOM000061454D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Choi, KW: AUTHOR [+2]

Abstract

This article describes a CMOS process sequence utilizing salicide to bridge a trench (vertical capacitor) and also provide for true isolation between gate, source and drain. Blanket vacuum deposition of a conducting layer is typically made over surfaces having a great deal of variation in topography. Problems arise because the thickness of the deposition on these differing topographies varies dramatically. Fig. 1 shows a typical CMOS device structure with all of the above-mentioned surface features. Fabricated on a silicon substrate 10 is a vertical trench 11 with an oxide insulator 12 on the sidewalls and bottom. The trench is filled with heavily doped polysilicon 13 and etched back to become as planar as possible.

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CMOS Process for Titanium Salicide Bridging of a Trench and Simultaneously Allowing for True Gate Isolation

This article describes a CMOS process sequence utilizing salicide to bridge a trench (vertical capacitor) and also provide for true isolation between gate, source and drain. Blanket vacuum deposition of a conducting layer is typically made over surfaces having a great deal of variation in topography. Problems arise because the thickness of the deposition on these differing topographies varies dramatically. Fig. 1 shows a typical CMOS device structure with all of the above-mentioned surface features. Fabricated on a silicon substrate 10 is a vertical trench 11 with an oxide insulator 12 on the sidewalls and bottom. The trench is filled with heavily doped polysilicon 13 and etched back to become as planar as possible. Due to all of the process variables, a step 14 of several hundred angstroms relative to the plane of the substrate 15 remains after etch back. The structure has diffused source 16 and drain 17 regions having topography planar upper surfaces 18. The polysilicon gate structure 19 has oxide sidewalls 20, whose slope is greater than 70 degrees, and an upper surface 21 which is planar. The structure is bounded on both sides by recessed oxide (ROX)
22. An evaporated blanket layer of titanium (approximately 1,000 angstroms) 23 is deposited on the above structure. Due to the various surface topographies, the layer of titanium is not of uniform thickness. If 2,000 angstroms of titanium is deposited, approximately 1,500 angstroms of titanium will be left on the planar surfaces, while approximately 680 angstroms of...