Browse Prior Art Database

Original Method to Diagnose a Fail in a NMOS LSSD Chain

IP.com Disclosure Number: IPCOM000061459D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Du Pasquier, M: AUTHOR [+2]

Abstract

In European Patent Application No. 83430043.6 (Publication Number 146661), a methodology has been disclosed to diagnose failures occurring in LSSD (Level Sensitive Scan Design) chains. This method was based on DC variations induced on Idd supply current during the loading of the chain. Since then, this method has been successfully improved, for better precision, on NMOS circuits. When an LSSD chain is set in the flush mode, that is, A and B clocks active and C inactive, a data applied on the scan input is transmitted immediately to the scan output with a delay equal to the sum of the propagation delays of all the string cells. The propagation of the data induces switching in the LSSD latches and in the logic surrounding them. If we display the supply current of the device under test (DUT), e.g.

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Original Method to Diagnose a Fail in a NMOS LSSD Chain

In European Patent Application No. 83430043.6 (Publication Number 146661), a methodology has been disclosed to diagnose failures occurring in LSSD (Level Sensitive Scan Design) chains. This method was based on DC variations induced on Idd supply current during the loading of the chain. Since then, this method has been successfully improved, for better precision, on NMOS circuits. When an LSSD chain is set in the flush mode, that is, A and B clocks active and C inactive, a data applied on the scan input is transmitted immediately to the scan output with a delay equal to the sum of the propagation delays of all the string cells. The propagation of the data induces switching in the LSSD latches and in the logic surrounding them. If we display the supply current of the device under test (DUT), e.g., a chip, on an oscilloscope, we can notice variations and spikes on the curve as long as the data has not reached the output, each spike being produced by each latch of the chain. The principle of this first version of the NMOS diagnostics was to compare a failing signature with the signature of a good DUT by overlapping them on a digital memory scope. When the failing signature became flat, it meant that the data had reached the fail state and couldn't propagate any more. If some reference spikes of the good signature had been previously identified, it was rather easy to interpolate between two of them to find the number of the failing latch. However, the precision of the diagnostics obtained with this method was within 3 latches. The great improvement was then found, which consists in using the shift clocks in the scan mode to synchronize the propagation of the data and so to know at any moment where the data was. The operation is slightly different: instead of tracing the latches by means of the transient spik...