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Xor-Controlled Chip Redundancy

IP.com Disclosure Number: IPCOM000061464D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+3]

Abstract

Computing machine self-repair can be enabled at either the chip or multi-chip module level through the application of redundancy techniques. This article discloses a means for accomplishing both computer self-repair and CIP (chip-in-place) testing functions through the automatic replacement of failing chips by redundant chips dotted together at both input and output nodes. In practice, non-functioning chips are replaced electrically by switching power from the failing chip to a quiescent chip. Chip redundancy on large multi-chip modules can be accomplished simply through the addition of an exclusive OR (XOR). The XOR's are used in conjunction with known power reduction circuits [1, 2] to turn power on or off to any or all chips, thereby providing logic-controlled power to the chips in the multi-chip module (MCM).

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Xor-Controlled Chip Redundancy

Computing machine self-repair can be enabled at either the chip or multi-chip module level through the application of redundancy techniques. This article discloses a means for accomplishing both computer self-repair and CIP (chip-in- place) testing functions through the automatic replacement of failing chips by redundant chips dotted together at both input and output nodes. In practice, non- functioning chips are replaced electrically by switching power from the failing chip to a quiescent chip. Chip redundancy on large multi-chip modules can be accomplished simply through the addition of an exclusive OR (XOR). The XOR's are used in conjunction with known power reduction circuits [1, 2] to turn power on or off to any or all chips, thereby providing logic-controlled power to the chips in the multi-chip module (MCM). One of the XOR inputs of each chip is connected to a common module control pin and through a 'pull-down' to a 'down' level. The other is connected both to individual EC pads and to addressing logic. The XOR inputs that are connected to addressing logic are held at an 'up' level, power is applied to all chips except the one or ones that are selected as shown in the Truth Table. The powered 'down' chips are the redundant chips that are dotted with active chips and can be powered 'up' under logic control to replace failing chips. Redundant chips may be selected to replace bad chips automatically as a result of error codes ge...