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Control Circuit for Hot Plugging a ROS Cartridge

IP.com Disclosure Number: IPCOM000061466D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Combs, JL: AUTHOR [+3]

Abstract

The electromechanical problem of contact bounce due to insertion and removal of a ROS (read-only storage) cartridge in a socket in an active computer is prevented through providing computer interrupt signals to a microprocessor upon insertion or removal of the ROS cartridge from its socket, creating a power-on reset signal only after contact bounce should be eliminated, and preventing a further computer interrupt signal until a predetermined period after the power-on reset signal is created. When a ROS cartridge is inserted or removed from a socket in an active computer, a CARDPDI* signal goes low due to a terminal being grounded so that the output of an AND gate 1 goes low.

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Control Circuit for Hot Plugging a ROS Cartridge

The electromechanical problem of contact bounce due to insertion and removal of a ROS (read-only storage) cartridge in a socket in an active computer is prevented through providing computer interrupt signals to a microprocessor upon insertion or removal of the ROS cartridge from its socket, creating a power-on reset signal only after contact bounce should be eliminated, and preventing a further computer interrupt signal until a predetermined period after the power-on reset signal is created. When a ROS cartridge is inserted or removed from a socket in an active computer, a CARDPDI* signal goes low due to a terminal being grounded so that the output of an AND gate 1 goes low. The other input to the AND gate 1 remains high at all times during insertion or removal of the ROS cartridge so that the output of the AND gate is the same as the CARDPDI* signal. The low signal from the AND gate 1 is supplied to RST input of a timer 2 to activate the timer 2. When activated, the timer 2 supplies a clock signal to a four-bit counter 3, which counts from zero to fifteen. The low signal from the AND gate 1 also is supplied to a CLR input of a flip-flop 4 to cause its Q output to go down since its PR input is high. The Q output from the flip-flop 4 is supplied through an inverter 5 to produce a high NMI88 signal to an Intel 8088 microprocessor to interrupt the 8088 microprocessor and allow the 8088 microprocessor to store the current state of the computer. The NMI88 signal must be held high for at least 150 microseconds and is accomplished by holding the NMI88 signal high for the first eight counts in the four-bit counter 3. This occurs even though the CARDPDI* signal goes up when the ROS cartridge is fully inserted or completely removed. The Q output from the flip-flop 4 also is supplied over a line 6 to an Intel 8051 microprocessor as an NMI51 signal. The low NMI51 signal to the 8051 microprocessor interrupts its operation. The Q output of the flip-flop 4 also is supplied to a PR input of a flip-flop 7. The low at the PR input of the flip-flop 7 causes its Q output to go up to enable the counter 3 to start to count. When the counter 3 completes eight counts, its OD output goes up. The OD signal is supplied through an inverter 8 and an AND gate 9 to a PR input of the flip-flop 4. The inverter 8 changes this high signal to a low; the low signal to the PR input of the flip-flop 4 causes its Q output to go up, whereby the NMI88 signal goes down and the NMI51 signal goes up. This results in both of the microprocessors no longer being interrupted. The other input to the AND gate 9 also is supplied...