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High Performance Clock Signal Generator

IP.com Disclosure Number: IPCOM000061467D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

DeFazio, JJ: AUTHOR

Abstract

This article describes a clock signal generator (also known as a "clock-chopper") circuit that generates an output pulse whose width is greater than one-half of the oscillator input cycle time (a 50% duty- cycle oscillator), while also being able to control the pulse to its off-state during system testing. Pulse generation is very critical in high speed digital systems. A reduction in statistical pulse-width variation, for example, allows for a reduction in system path lengths with a corresponding improvement in system performance. Fig. 1 illustrates a method for generating a pulse that is greater in width than one half of the input cycle time. A 50% duty cycle pulse is typically used as an input source.

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High Performance Clock Signal Generator

This article describes a clock signal generator (also known as a "clock- chopper") circuit that generates an output pulse whose width is greater than one- half of the oscillator input cycle time (a 50% duty- cycle oscillator), while also being able to control the pulse to its off-state during system testing. Pulse generation is very critical in high speed digital systems. A reduction in statistical pulse-width variation, for example, allows for a reduction in system path lengths with a corresponding improvement in system performance. Fig. 1 illustrates a method for generating a pulse that is greater in width than one half of the input cycle time. A 50% duty cycle pulse is typically used as an input source. The circuit, however, uses two edges of the input (consecutive rises and fall edges) to generate the output, the resulting output pulse therefore being dependent both upon input pulse variation and cycle time. An alternative implementation is disclosed in Fig. 2, in which only one edge of the input pulse is used to generate the output. This results in a reduction in the output pulse variation, and the active level is independent of input cycle time as well. This implementation will also satisfy a requirement that the steady-state value of the "clock chopper" be "off". Fig. 3 shows that if a logical '1' or '0' is applied at the input, the resultant output is always a '1', which means that the pulse is inactive or disabled,...