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Developmental Support System for Hierarchical Multi-Level Logic Design

IP.com Disclosure Number: IPCOM000061477D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Rodriguez, JR: AUTHOR [+2]

Abstract

Described is a development support system designed to reduce the overall effort required to develop complex logic modules used in computer systems. The system consists of three parts: 1. A hierarchical model for the organization of hardware in a structured top-down design. 2. A design methodology that supports the view of the hierarchical model. 3. Developmental tools based on the model which fully supports the design methodology design described herein. The design methodology is to use the top-down approach with a functional decomposition strategy following each design step in a hierarchical manner, so that each progressive step can deal with the increased design complexity. The flow chart in Fig. 1 shows the hierarchical design steps and accomplishes the following: 1.

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Developmental Support System for Hierarchical Multi-Level Logic Design

Described is a development support system designed to reduce the overall effort required to develop complex logic modules used in computer systems. The system consists of three parts: 1. A hierarchical model for the organization of hardware in a structured top-down design. 2. A design methodology that supports the view of the hierarchical model. 3. Developmental tools based on the model which fully supports the design methodology design described herein. The design methodology is to use the top-down approach with a functional decomposition strategy following each design step in a hierarchical manner, so that each progressive step can deal with the increased design complexity. The flow chart in Fig. 1 shows the hierarchical design steps and accomplishes the following: 1. Establishes architectural requirements of interface operations/sequences. 2. Establishes the timing requirements for interface sequences. 3. Establishes the design data path. 4. Establishes the design control interface to the data path. 5. Establishes the logic partitioning for the design of each logic block. 6. Integrates component logic blocks. 7. Performs functional simulation and in-circuit emulation. 8. Verifies the design at all levels. 9. Generates the documentation needed to build the integrated circuits. The advantages of functional simulation provide proof of behavioral descriptions (flowcharts, DL/HML design language for hierarchical multi-level logic) before any gate level design is attempted. Therefore, functional errors and changes are easily corrected. The concept of the hierarchical multi-level design approach can be visualized in the model in Fig. 2 where each level communicates with a subordinate block through an interface or link 1. The level 0 block 3 is comprised of data path elements such as registers, timers and counters, and is subordinate to control units 2 at higher levels in the hierarchy. Block 10, usually a microprocessor, represents the highest level in the hierarchy. Any level blocks 11 beyond N consist of software modules. Levels 1...